gw.syr

来自「基于FPGA的波束成型」· SYR 代码 · 共 856 行 · 第 1/5 页

 
Analyzing module <muxe>.
Module <muxe> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mult>.
    Related source file is "../complexmul.v".
WARNING:Xst:1780 - Signal <dj> is never used or assigned.
    Found 1-bit register for signal <rdy>.
    Found 32-bit register for signal <out>.
    Found 16x16-bit multiplier for signal <$n0002> created at line 105.
    Found 16-bit adder for signal <$n0004> created at line 94.
    Found 16-bit adder for signal <$n0005> created at line 100.
    Found 32-bit adder for signal <$n0006> created at line 109.
    Found 16-bit register for signal <ain>.
    Found 16-bit register for signal <bin>.
    Found 32-bit register for signal <outab>.
    Found 1-bit xor2 for signal <tk>.
    Summary:
	inferred  97 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <mult> synthesized.


Synthesizing Unit <jiewei>.
    Related source file is "../cutbit/jiewei.v".
WARNING:Xst:647 - Input <ai<9:0>> is never used.
WARNING:Xst:647 - Input <ar<9:0>> is never used.
    Found 16-bit register for signal <qi>.
    Found 16-bit register for signal <qr>.
    Found 1-bit register for signal <rdy>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <jiewei> synthesized.


Synthesizing Unit <complexmul>.
    Related source file is "../complexmul.v".
    Found 32-bit subtractor for signal <$n0000> created at line 35.
    Found 32-bit adder for signal <$n0001> created at line 36.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <complexmul> synthesized.


Synthesizing Unit <muxe>.
    Related source file is "muxe.v".
Unit <muxe> synthesized.


Synthesizing Unit <eexy>.
    Related source file is "eexy.v".
    Found 16-bit adder for signal <$n0000> created at line 33.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <eexy> synthesized.


Synthesizing Unit <gw>.
    Related source file is "gw.v".
    Found 16-bit register for signal <wn0i>.
    Found 16-bit register for signal <wn1i>.
    Found 16-bit register for signal <wn0r>.
    Found 16-bit register for signal <wn2i>.
    Found 16-bit register for signal <wn1r>.
    Found 16-bit register for signal <wn3i>.
    Found 16-bit register for signal <wn2r>.
    Found 16-bit register for signal <wn4i>.
    Found 16-bit register for signal <wn3r>.
    Found 16-bit register for signal <wn5i>.
    Found 16-bit register for signal <wn4r>.
    Found 16-bit register for signal <wn6i>.
    Found 16-bit register for signal <wn5r>.
    Found 16-bit register for signal <wn7i>.
    Found 16-bit register for signal <wn6r>.
    Found 16-bit register for signal <wn7r>.
    Found 1-bit register for signal <rdy>.
    Found 16-bit adder for signal <$n0001> created at line 56.
    Found 16-bit adder for signal <$n0002> created at line 57.
    Found 16-bit adder for signal <$n0003> created at line 58.
    Found 16-bit adder for signal <$n0004> created at line 59.
    Found 16-bit adder for signal <$n0005> created at line 60.
    Found 16-bit adder for signal <$n0006> created at line 61.
    Found 16-bit adder for signal <$n0007> created at line 62.
    Found 16-bit adder for signal <$n0008> created at line 63.
    Found 16-bit adder for signal <$n0009> created at line 65.
    Found 16-bit adder for signal <$n0010> created at line 66.
    Found 16-bit adder for signal <$n0011> created at line 67.
    Found 16-bit adder for signal <$n0012> created at line 68.
    Found 16-bit adder for signal <$n0013> created at line 69.
    Found 16-bit adder for signal <$n0014> created at line 70.
    Found 16-bit adder for signal <$n0015> created at line 71.
    Found 16-bit adder for signal <$n0016> created at line 72.
    Summary:
	inferred 257 D-type flip-flop(s).
	inferred  16 Adder/Subtractor(s).
Unit <gw> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
    Found registered multiplier on signal <_n0002>:
	- 1 register level(s) found in a register connected to the multiplier macro ouput.
	  Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                      : 64
 16x16-bit registered multiplier   : 64
# Adders/Subtractors               : 241
 16-bit adder                      : 145
 32-bit adder                      : 80
 32-bit subtractor                 : 16
# Registers                        : 321
 1-bit register                    : 81
 16-bit register                   : 176
 32-bit register                   : 64
# Xors                             : 64
 1-bit xor2                        : 64

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <gw> ...

Optimizing unit <eexy> ...

Optimizing unit <jiewei> ...

Optimizing unit <mult> ...

Optimizing unit <complexmul> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
WARNING:Xst:1293 - FF/Latch  <mue1/mw3/u4/ain_15> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_0> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_1> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_2> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_3> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_4> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_5> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_6> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_7> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_8> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_9> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_10> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_11> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_12> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_13> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u4/ain_14> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u2/ain_15> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u2/ain_0> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u2/ain_1> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u2/ain_2> has a constant value of 0 in block <gw>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <mue1/mw3/u2/ain_3> has a constant value of 0 in block <gw>.