eexy.syr

基于FPGA的波束成型

Found area constraint ratio of 100 (+ 5) on block eexy, actual ratio is 82.
Register <mulw8/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw1/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw2/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw3/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw4/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw5/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw6/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw7/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw6/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw5/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw4/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw3/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw2/u4/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw7/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw8/u2/ain_0> equivalent to <mulw1/u4/ain_0> has been removed
Register <mulw1/u1/bin_0> equivalent to <mulw1/u4/bin_0> has been removed
Register <mulw7/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw1/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw2/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw3/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw4/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw5/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw6/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw7/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw6/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw5/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw4/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw3/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw2/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw8/u3/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw1/u2/bin_0> equivalent to <mulw1/u3/bin_0> has been removed
Register <mulw2/u1/bin_0> equivalent to <mulw2/u4/bin_0> has been removed
Register <mulw2/u2/bin_0> equivalent to <mulw2/u3/bin_0> has been removed
Register <mulw3/u1/bin_0> equivalent to <mulw3/u4/bin_0> has been removed
Register <mulw3/u2/bin_0> equivalent to <mulw3/u3/bin_0> has been removed
Register <mulw4/u1/bin_0> equivalent to <mulw4/u4/bin_0> has been removed
Register <mulw4/u2/bin_0> equivalent to <mulw4/u3/bin_0> has been removed
Register <mulw5/u1/bin_0> equivalent to <mulw5/u4/bin_0> has been removed
Register <mulw5/u2/bin_0> equivalent to <mulw5/u3/bin_0> has been removed
Register <mulw6/u1/bin_0> equivalent to <mulw6/u4/bin_0> has been removed
Register <mulw6/u2/bin_0> equivalent to <mulw6/u3/bin_0> has been removed
Register <mulw7/u1/bin_0> equivalent to <mulw7/u4/bin_0> has been removed
Register <mulw7/u2/bin_0> equivalent to <mulw7/u3/bin_0> has been removed
Register <mulw8/u2/bin_0> equivalent to <mulw8/u3/bin_0> has been removed
Register <mulw8/u1/ain_0> equivalent to <mulw1/u3/ain_0> has been removed
Register <mulw8/u1/bin_0> equivalent to <mulw8/u4/bin_0> has been removed
FlipFlop mulw1/u4/rdy has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : eexy.ngr
Top Level Output File Name         : eexy
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 547

Macro Statistics :
# Registers                        : 152
#      1-bit register              : 40
#      16-bit register             : 80
#      32-bit register             : 32
# Adders/Subtractors               : 113
#      16-bit adder                : 65
#      32-bit adder                : 40
#      32-bit subtractor           : 8
# Multipliers                      : 32
#      16x16-bit registered multiplier: 32

Cell Usage :
# BELS                             : 10002
#      BUF                         : 4
#      GND                         : 1
#      INV                         : 1970
#      LUT1                        : 97
#      LUT2                        : 321
#      LUT2_L                      : 520
#      LUT3                        : 936
#      LUT3_L                      : 32
#      LUT4                        : 1138
#      LUT4_D                      : 8
#      LUT4_L                      : 40
#      MUXCY                       : 2463
#      VCC                         : 1
#      XORCY                       : 2471
# FlipFlops/Latches                : 2269
#      FDE                         : 978
#      FDR                         : 1291
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 546
#      IBUF                        : 289
#      OBUF                        : 257
# MULTs                            : 32
#      MULT18X18S                  : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                    2839  out of   3584    79%  
 Number of Slice Flip Flops:          2269  out of   7168    31%  
 Number of 4 input LUTs:              3092  out of   7168    43%  
 Number of bonded IOBs:                547  out of    141   387% (*) 
 Number of MULT18X18s:                  32  out of     16   200% (*) 
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 2301  |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.287ns (Maximum Frequency: 88.601MHz)
   Minimum input arrival time before clock: 12.626ns
   Maximum output required time after clock: 9.126ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.287ns (frequency: 88.601MHz)
  Total number of paths / destination ports: 857328 / 2568
-------------------------------------------------------------------------
Delay:               11.287ns (Levels of Logic = 35)
  Source:            mulw8/u3/out_0 (FF)
  Destination:       jw8/rdy (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: mulw8/u3/out_0 to jw8/rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  mulw8/u3/out_0 (mulw8/u3/out_0)
     LUT2_L:I0->LO         1   0.479   0.000  mulw8/complexmul__n0001<0>lut (mulw8/N4)
     MUXCY:S->O            1   0.435   0.000  mulw8/complexmul__n0001<0>cy (mulw8/complexmul__n0001<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<1>cy (mulw8/complexmul__n0001<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<2>cy (mulw8/complexmul__n0001<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<3>cy (mulw8/complexmul__n0001<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<4>cy (mulw8/complexmul__n0001<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<5>cy (mulw8/complexmul__n0001<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<6>cy (mulw8/complexmul__n0001<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<7>cy (mulw8/complexmul__n0001<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<8>cy (mulw8/complexmul__n0001<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<9>cy (mulw8/complexmul__n0001<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<10>cy (mulw8/complexmul__n0001<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<11>cy (mulw8/complexmul__n0001<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<12>cy (mulw8/complexmul__n0001<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<13>cy (mulw8/complexmul__n0001<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<14>cy (mulw8/complexmul__n0001<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<15>cy (mulw8/complexmul__n0001<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<16>cy (mulw8/complexmul__n0001<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<17>cy (mulw8/complexmul__n0001<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<18>cy (mulw8/complexmul__n0001<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<19>cy (mulw8/complexmul__n0001<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<20>cy (mulw8/complexmul__n0001<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<21>cy (mulw8/complexmul__n0001<21>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<22>cy (mulw8/complexmul__n0001<22>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<23>cy (mulw8/complexmul__n0001<23>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<24>cy (mulw8/complexmul__n0001<24>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<25>cy (mulw8/complexmul__n0001<25>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<26>cy (mulw8/complexmul__n0001<26>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<27>cy (mulw8/complexmul__n0001<27>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<28>cy (mulw8/complexmul__n0001<28>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mulw8/complexmul__n0001<29>cy (mulw8/complexmul__n0001<29>_cyo)
     XORCY:CI->O           1   0.786   0.976  mulw8/complexmul__n0001<30>_xor (mulw8/_n0001<30>)
     LUT4:I0->O            1   0.479   0.976  mulw8/_n0003286 (CHOICE476)
     LUT4:I0->O            4   0.479   1.074  mulw8/_n0003366 (CHOICE496)
     LUT4:I0->O            9   0.479   0.955  jw8/rdy_N01_3 (jw8/rdy_N012)
     FDR:R                     0.892          jw8/qr_2
    ----------------------------------------
    Total                     11.287ns (6.265ns logic, 5.022ns route)
                                       (55.5% logic, 44.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 38103 / 3975
-------------------------------------------------------------------------
Offset:              12.626ns (Levels of Logic = 20)
  Source:            eei<0> (PAD)
  Destination:       mulw4/u4/out_31 (FF)
  Destination Clock: clk rising

  Data Path: eei<0> to mulw4/u4/out_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            18   0.715   1.499  eei_0_IBUF (eei_0_IBUF)
     LUT1:I0->O            1   0.479   0.000  eei_0_IBUF_rt (eei_0_IBUF_rt)
     MUXCY:S->O            1   0.435   0.000  eexy__n0000<0>cy (eexy__n0000<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<1>cy (eexy__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<2>cy (eexy__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<3>cy (eexy__n0000<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<4>cy (eexy__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<5>cy (eexy__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<6>cy (eexy__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<7>cy (eexy__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<8>cy (eexy__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<9>cy (eexy__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<10>cy (eexy__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<11>cy (eexy__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<12>cy (eexy__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eexy__n0000<13>cy (eexy__n0000<13>_cyo)
     MUXCY:CI->O           0   0.056   0.000  eexy__n0000<14>cy (eexy__n0000<14>_cyo)
     XORCY:CI->O         376   0.786   3.250  eexy__n0000<15>_xor (_n0000<15>)
     BUF:I->O            377   0.479   3.550  eexy__n0000<15>_xor_1 (eexy__n0000<15>_xor_1)
     LUT4:I0->O            1   0.479   0.000  mulw8/u4/_n0003<9>1 (mulw8/u4/_n0003<9>)
     FDR:D                     0.176          mulw8/u4/out_9
    ----------------------------------------
    Total                     12.626ns (4.326ns logic, 8.300ns route)
                                       (34.3% logic, 65.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 264 / 257
-------------------------------------------------------------------------
Offset:              9.126ns (Levels of Logic = 3)
  Source:            jw1/rdy (FF)
  Destination:       rdy (PAD)
  Source Clock:      clk rising

  Data Path: jw1/rdy to rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.626   0.976  jw1/rdy (jw1/rdy)
     LUT4:I0->O            1   0.479   0.976  rdy4 (CHOICE399)
     LUT2:I0->O            1   0.479   0.681  rdy10 (rdy_OBUF)
     OBUF:I->O                 4.909          rdy_OBUF (rdy)
    ----------------------------------------
    Total                      9.126ns (6.493ns logic, 2.633ns route)
                                       (71.2% logic, 28.8% route)

=========================================================================
CPU : 103.41 / 104.52 s | Elapsed : 103.00 / 104.00 s
 
--> 

Total memory usage is 134404 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   24 (   0 filtered)
Number of infos    :    0 (   0 filtered)