cutbit.gfl

基于FPGA的波束成型

# XST (Creating Lso File) : 
jiewei.lso
# xst flow : RunXST
jiewei_summary.html
# xst flow : RunXST
jiewei.syr
jiewei.prj
jiewei.sprj
jiewei.ana
jiewei.stx
jiewei.cmd_log
jiewei.ngc
jiewei.ngr
# Bencher : Creating project file
jieweiwave_bencher.prj
# ProjNav -> New Source -> TBW
jieweiwave.vhw
jieweiwave.ano
jieweiwave.tfw
jieweiwave.ant
# Bencher : Creating project file
jieweiwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
jieweiwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
jieweiwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
jieweiwave_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jieweiwave.vhw
jieweiwave.ano
jieweiwave.tfw
jieweiwave.ant
# ModelSim : Simulate Behavioral Verilog Model
jieweiwave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
jiewei.lso
# xst flow : RunXST
jiewei_summary.html
# xst flow : RunXST
jiewei.syr
jiewei.prj
jiewei.sprj
jiewei.ana
jiewei.stx
jiewei.cmd_log
jiewei.ngc
jiewei.ngr