jieweiwave.tbw

基于FPGA的波束成型

version 3
f:\myfpga\xilinx\cutbit\jiewei.v
jiewei
VERILOG
VERILOG
jieweiwave.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ai
clk
ar
clk
qi
clk
qr
clk
rdy
clk
start
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
qi_DIFF
qr_DIFF
rdy_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
start
ai
ar
rdy
qi
qr
SIGNAL_ORDER_END
-X-X-X-