jieweiwave.tfw

基于FPGA的波束成型

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.03i
//  \   \         Application : ISE Foundation
//  /   /         Filename : jieweiwave.tfw
// /___/   /\     Timestamp : Sat Jun 02 10:39:12 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: jieweiwave
//Device: Xilinx
//
`timescale 1ns/1ps

module jieweiwave;
    reg [31:0] ar = 32'b00000000000000000000000000000000;
    reg [31:0] ai = 32'b00000000000000000000000000000000;
    wire [15:0] qr;
    wire [15:0] qi;
    reg clk = 1'b0;
    reg start = 1'b0;
    wire rdy;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    jiewei UUT (
        .ar(ar),
        .ai(ai),
        .qr(qr),
        .qi(qi),
        .clk(clk),
        .start(start),
        .rdy(rdy));

        integer TX_ERROR = 0;
        
        initial begin  // Open the results file...
            #10200 // Final time:  10200 ns
            if (TX_ERROR == 0) begin
                $display("No errors or warnings.");
                end else begin
                    $display("%d errors found in simulation.", TX_ERROR);
                    end
                    $stop;
                end

                initial begin
                    // -------------  Current Time:  285ns
                    #285;
                    ar = 32'b00000000011000000000000000000000;
                    ai = 32'b00000000010100000000000000000000;
                    // -------------------------------------
                    // -------------  Current Time:  485ns
                    #200;
                    start = 1'b1;
                    // -------------------------------------
                end

                task CHECK_qr;
                    input [15:0] NEXT_qr;

                    #0 begin
                        if (NEXT_qr !== qr) begin
                            $display("Error at time=%dns qr=%b, expected=%b", $time, qr, NEXT_qr);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_qi;
                    input [15:0] NEXT_qi;

                    #0 begin
                        if (NEXT_qi !== qi) begin
                            $display("Error at time=%dns qi=%b, expected=%b", $time, qi, NEXT_qi);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_rdy;
                    input NEXT_rdy;

                    #0 begin
                        if (NEXT_rdy !== rdy) begin
                            $display("Error at time=%dns rdy=%b, expected=%b", $time, rdy, NEXT_rdy);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask

            endmodule