complexmul.v

基于FPGA的波束成型

//本复数乘法器需要四个时钟周期

`timescale 1ns / 1ps
module complexmul(ar,ai,br,bi,qr,qi,clk,start,rdy);

//parameter wid=16;

input[15:0] ar,br,ai,bi;
input start,clk;
output[31:0] qr,qi;
output rdy;

wire[31:0] temp0,temp1,temp2,temp3;
reg[31:0] qr=32'b0,qi=32'b0;
reg rdy;
wire rdy1,rdy2,rdy3,rdy4;


mult u1(ar,br,temp0,clk,start,rdy1);
mult u2(ai,bi,temp1,clk,start,rdy2);
mult u3(ar,bi,temp2,clk,start,rdy3);
mult u4(ai,br,temp3,clk,start,rdy4);	

/*
assign qr=temp0-temp1;
assign qi=temp2+temp3;
assign rdy=rdy1*rdy2*rdy3*rdy4;
*/

always @ (temp0 or temp1 or temp2 or temp3)
	begin
		if(rdy1&&rdy2&&rdy3&&rdy4)
			begin
				qr<=temp0-temp1;
				qi<=temp2+temp3;
				//rdy<=1;
			end
		else
			begin
				qr<=32'b0;
				qi<=32'b0;
				//rdy<=0;
			end
			
	end
	
always @ (qr or qi)
	begin
		if(qr||qi)
			rdy<=1;
		else
			rdy<=0;
	end

endmodule

//--------------------------------------------------------------------
module mult(a,b,out,clk,start,rdy);

output[31:0] out;
output rdy;
//output done;
input[15:0] a,b;
input clk,start;
reg[31:0] out;

reg[31:0] outab=32'b0;
wire tk;

reg dj,rdy;
//reg done;
reg[15:0] ain=16'b00000000;
reg[15:0] bin=16'b00000000;



initial
begin
	dj=0;
	rdy=0;
//	done=0;
end
assign tk=a[15]^b[15];


always @ (posedge clk)
	begin
		if(start)
			begin
				
				if(a[15])
					begin
						ain<=(~a)+16'b0000000000000001;
					end
				else
					ain<=a;
					
				if(b[15])
					bin<=(~b)+16'b0000000000000001;
				else
					bin<=b;
					
				
				outab<=ain*bin;
				
				if(tk)
					begin
						out<=(~outab)+16'b0000000000000001;
						rdy<=1;
					end
				else
					begin
						out<=outab;
						rdy<=1;
					end
				
			end
			
		else
			begin
				out<=32'b0;
				rdy<=0;
			end
	end

/*
always @(dj)

	begin 
		if(start)
			begin
				outab<=ain*bin;
				if(tk)
					begin
						out<=(~outab)+16'b0000000000000001;
						rdy<=1;
					end
				else
					begin
						out<=outab;
						rdy<=1;
					end
			end
			
	end
	*/
				
endmodule