gee.v

来自「基于FPGA的波束成型」· Verilog 代码 · 共 32 行

//ee(k)
//需要2个CLK
module gee(der,dei,ykr,yki,eer,eei,clk,start,rdy);

input[15:0] der,dei,ykr,yki;
input clk,start;

output[15:0] eer,eei;
output rdy;

reg rdy=0;
reg[15:0] eer,eei;

always @ (posedge clk)
	begin
		if(start)
			begin
				eer<=der-ykr;
				eei<=dei-yki;
				rdy<=1;
			end
		else
			begin
				eer<=16'b0;
				eei<=16'b0;
				rdy<=0;
			end
	end


endmodule