sig.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    21:18:34 06/03/07
// Design Name:    
// Module Name:    sig
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module sig(mux2,der,dei,yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,clk,start,rdyw);

output[15:0] mux2,der,dei,yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i;
input clk,start;

reg[9:0] ct=0;
reg rdyw=0;	//w总输出时的使能信号

initial
mux2=8;


always @ (posedge clk)
	begin
		if(start||rdyw)
			begin
				ct<=ct+1;
				casez(ct):
				1: 





				 256:

				 default: start<=0;
			end
	end



endmodule