zh32.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    19:16:32 06/03/07
// Design Name:    
// Module Name:    zh32
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module zh32(a0r,a0i,a1r,a1i,a2r,a2i,a3r,a3i,a4r,a4i,a5r,a5i,a6r,a6i,a7r,a7i,
				q0r,q0i,q1r,q1i,q2r,q2i,q3r,q3i,q4r,q4i,q5r,q5i,q6r,q6i,q7r,q7i,clk,start,rdy);

input[15:0] a0r,a0i,a1r,a1i,a2r,a2i,a3r,a3i,a4r,a4i,a5r,a5i,a6r,a6i,a7r,a7i;
input clk,start;
output[31:0] q0r,q0i,q1r,q1i,q2r,q2i,q3r,q3i,q4r,q4i,q5r,q5i,q6r,q6i,q7r,q7i;
output rdy;

reg[31:0] q0r,q0i,q1r,q1i,q2r,q2i,q3r,q3i,q4r,q4i,q5r,q5i,q6r,q6i,q7r,q7i;
reg rdy;
reg[15:0] aa;

initial
 aa=16'b1111111111111111;

always @ (posedge clk)
	begin
		if(start)
			begin
				if(a0r[15]==1)
					begin
					q0r<={aa,a0r};
				//	rdy<=1;
					end
				else
					q0r<=a0r;
				//	rdy<=1;

				if(a0i[15]==1)
					q0i<={aa,a0i};
				//	rdy<=1;
				else
					q0i<=a0i;
				//	rdy<=1;

				if(a1r[15]==1)
					q1r<={aa,a1r};
				//	rdy<=1;
				else
					q1r<=a1r;
				//	rdy<=1;

				if(a1i[15]==1)
					q1i<={aa,a1i};
				//	rdy<=1;
				else
					q1i<=a1i;
				//	rdy<=1;

				if(a2r[15]==1)
					q2r<={aa,a2r};
				//	rdy<=1;
				else
					q2r<=a2r;
				//	rdy<=1;

				if(a2i[15]==1)
					q2i<={aa,a2i};
				//	rdy<=1;
				else
					q2i<=a2i;
				//	rdy<=1;

				if(a3r[15]==1)
					q3r<={aa,a3r};
				//	rdy<=1;
				else
					q3r<=a3r;
				//	rdy<=1;

				if(a3i[15]==1)
					q3i<={aa,a3i};
				//	rdy<=1;
				else
					q3i<=a3i;
				//	rdy<=1;

				if(a4r[15]==1)
					q4r<={aa,a4r};
				//	rdy<=1;
				else
					q4r<=a4r;
				//	rdy<=1;

				if(a4i[15]==1)
					q4i<={aa,a4i};
				//	rdy<=1;
				else
					q4i<=a4i;
				//	rdy<=1;


					if(a5r[15]==1)
					q5r<={aa,a5r};
				//	rdy<=1;
				else
					q5r<=a5r;
				//	rdy<=1;

					if(a5i[15]==1)
					q5i<={aa,a5i};
				//	rdy<=1;
				else
					q5i<=a5i;
				//	rdy<=1;

					if(a6r[15]==1)
					q6r<={aa,a6r};
				//	rdy<=1;
				else
					q6r<=a6r;
				//	rdy<=1;

					if(a6i[15]==1)
					q6i<={aa,a6i};
				//rdy<=1;
				else
					q6i<=a6i;
					//rdy<=1;

					if(a7r[15]==1)
					q7r<={aa,a7r};
				//	rdy<=1;
				else
					q7r<=a7r;
					//rdy<=1;

					if(a7i[15]==1)
					q7i<={aa,a7i};
					//rdy<=1;
				else
					q7i<=a7i;

					rdy<=1;	
			end

		else
			begin
				rdy<=0;

				q0r<=32'b0;
				q0i<=32'b0;
				q1r<=32'b0;
				q1i<=32'b0;
				q2r<=32'b0;
				q2i<=32'b0;
				q3r<=32'b0;
				q3i<=32'b0;
				q4r<=32'b0;
				q4i<=32'b0;
				q5r<=32'b0;
				q5i<=32'b0;
				q6r<=32'b0;
				q6i<=32'b0;
				q7r<=32'b0;
				q7i<=32'b0;
			end
	end



endmodule