gwt.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    22:48:44 06/02/07
// Design Name:    
// Module Name:    gwt
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//本模块计算权值W。	需要15个周期
// 
////////////////////////////////////////////////////////////////////////////////
module gwt(mux2,der,dei,w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
				yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
				wout0r,wout0i,wout1r,wout1i,wout2r,wout2i,wout3r,wout3i,wout4r,wout4i,wout5r,wout5i,wout6r,wout6i,wout7r,wout7i,
				clk,start,rdy);

input[15:0] mux2,der,dei;
input[15:0]	w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i;
input[15:0] yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i;
input clk,start;

output[15:0] wout0r,wout0i,wout1r,wout1i,wout2r,wout2i,wout3r,wout3i,wout4r,wout4i,wout5r,wout5i,wout6r,wout6i,wout7r,wout7i;
output rdy;

wire[15:0] ykr,yki,eer,eei;
wire rdy1,rdy2,rdy3;
reg rdy=0;

//reg rdy=0;


gyk yk(w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
		yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
		ykr,yki,clk,start,rdy1);

gee eek(der,dei,ykr,yki,eer,eei,clk,rdy1,rdy2);

gw ww(mux2,eer,eei,
			w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
			yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
			wout0r,wout0i,wout1r,wout1i,wout2r,wout2i,wout3r,wout3i,wout4r,wout4i,wout5r,wout5i,wout6r,wout6i,wout7r,wout7i,
			clk,rdy2,rdy3);

always @ (posedge clk)
	begin
		if(start&&rdy3)
			begin
				rdy<=1;
			end
		else
			rdy<=0;
			
	end


endmodule