jiewei2.v

来自「基于FPGA的波束成型」· Verilog 代码 · 共 47 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:06:29 06/03/07
// Design Name:    
// Module Name:    jiewei2
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module jiewei2(ar,ai,qr,qi,clk,start,rdy);
input[63:0] ar,ai;
input clk,start;
output[15:0] qr,qi;
output rdy;

reg[15:0] qr,qi;
reg rdy;

always @ (posedge clk)
begin
	if(start)
		begin
			qr<=ar>>24;
			qi<=ai>>24;
			rdy<=1;
		end
	else
		begin
			qr<=16'b0;
			qi<=16'b0;
			rdy<=0;
		end
end

endmodule