gwt.syr

基于FPGA的波束成型

WARNING:Xst:854 - "cmpmul32.v" line 80: Ignored initial statement.
Module <mult32> is correct for synthesis.
 
Analyzing module <jiewei2>.
Module <jiewei2> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mult32>.
    Related source file is "cmpmul32.v".
WARNING:Xst:1780 - Signal <dj> is never used or assigned.
    Found 1-bit register for signal <rdy>.
    Found 64-bit register for signal <out>.
    Found 32x32-bit multiplier for signal <$n0002> created at line 107.
    Found 32-bit adder for signal <$n0004> created at line 96.
    Found 32-bit adder for signal <$n0005> created at line 102.
    Found 64-bit adder for signal <$n0006> created at line 111.
    Found 32-bit register for signal <ain>.
    Found 32-bit register for signal <bin>.
    Found 64-bit register for signal <outab>.
    Found 1-bit xor2 for signal <tk>.
    Summary:
	inferred 193 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <mult32> synthesized.


Synthesizing Unit <jiewei2>.
    Related source file is "jiewei2.v".
WARNING:Xst:647 - Input <ai<23:0>> is never used.
WARNING:Xst:647 - Input <ar<23:0>> is never used.
    Found 16-bit register for signal <qi>.
    Found 16-bit register for signal <qr>.
    Found 1-bit register for signal <rdy>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <jiewei2> synthesized.


Synthesizing Unit <cmpmul32>.
    Related source file is "cmpmul32.v".
    Found 64-bit subtractor for signal <$n0000> created at line 37.
    Found 64-bit adder for signal <$n0001> created at line 38.
    Found 64-bit comparator not equal for signal <$n0004>.
    Found 64-bit comparator not equal for signal <$n0005>.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <cmpmul32> synthesized.


Synthesizing Unit <zh32>.
    Related source file is "zh32.v".
WARNING:Xst:653 - Signal <aa> is used but never assigned. Tied to value 0000000000000000.
    Found 32-bit register for signal <q0i>.
    Found 32-bit register for signal <q1i>.
    Found 32-bit register for signal <q0r>.
    Found 32-bit register for signal <q2i>.
    Found 32-bit register for signal <q1r>.
    Found 32-bit register for signal <q3i>.
    Found 32-bit register for signal <q2r>.
    Found 32-bit register for signal <q4i>.
    Found 32-bit register for signal <q3r>.
    Found 32-bit register for signal <q5i>.
    Found 32-bit register for signal <q4r>.
    Found 32-bit register for signal <q6i>.
    Found 32-bit register for signal <q5r>.
    Found 32-bit register for signal <q7i>.
    Found 32-bit register for signal <q6r>.
    Found 32-bit register for signal <q7r>.
    Found 1-bit register for signal <rdy>.
    Summary:
	inferred 513 D-type flip-flop(s).
Unit <zh32> synthesized.


Synthesizing Unit <eexy>.
    Related source file is "../wopt/eexy.v".
    Found 32-bit adder for signal <$n0000> created at line 57.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <eexy> synthesized.


Synthesizing Unit <muxe>.
    Related source file is "../wopt/muxe.v".
Unit <muxe> synthesized.


Synthesizing Unit <mult>.
    Related source file is "../complexmul.v".
WARNING:Xst:1780 - Signal <dj> is never used or assigned.
    Found 1-bit register for signal <rdy>.
    Found 32-bit register for signal <out>.
    Found 16x16-bit multiplier for signal <$n0002> created at line 105.
    Found 16-bit adder for signal <$n0004> created at line 94.
    Found 16-bit adder for signal <$n0005> created at line 100.
    Found 32-bit adder for signal <$n0006> created at line 109.
    Found 16-bit register for signal <ain>.
    Found 16-bit register for signal <bin>.
    Found 32-bit register for signal <outab>.
    Found 1-bit xor2 for signal <tk>.
    Summary:
	inferred  97 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <mult> synthesized.


Synthesizing Unit <jiewei>.
    Related source file is "../cutbit/jiewei.v".
WARNING:Xst:647 - Input <ai<11:0>> is never used.
WARNING:Xst:647 - Input <ar<11:0>> is never used.
    Found 16-bit register for signal <qi>.
    Found 16-bit register for signal <qr>.
    Found 1-bit register for signal <rdy>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <jiewei> synthesized.


Synthesizing Unit <complexmul>.
    Related source file is "../complexmul.v".
    Found 32-bit subtractor for signal <$n0000> created at line 35.
    Found 32-bit adder for signal <$n0001> created at line 36.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <complexmul> synthesized.


Synthesizing Unit <gw>.
    Related source file is "../wopt/gw.v".
    Found 16-bit register for signal <wn0i>.
    Found 16-bit register for signal <wn1i>.
    Found 16-bit register for signal <wn0r>.
    Found 16-bit register for signal <wn2i>.
    Found 16-bit register for signal <wn1r>.
    Found 16-bit register for signal <wn3i>.
    Found 16-bit register for signal <wn2r>.
    Found 16-bit register for signal <wn4i>.
    Found 16-bit register for signal <wn3r>.
    Found 16-bit register for signal <wn5i>.
    Found 16-bit register for signal <wn4r>.
    Found 16-bit register for signal <wn6i>.
    Found 16-bit register for signal <wn5r>.
    Found 16-bit register for signal <wn7i>.
    Found 16-bit register for signal <wn6r>.
    Found 16-bit register for signal <wn7r>.
    Found 1-bit register for signal <rdy>.
    Found 16-bit adder for signal <$n0001> created at line 56.
    Found 16-bit adder for signal <$n0002> created at line 57.
    Found 16-bit adder for signal <$n0003> created at line 58.
    Found 16-bit adder for signal <$n0004> created at line 59.
    Found 16-bit adder for signal <$n0005> created at line 60.
    Found 16-bit adder for signal <$n0006> created at line 61.
    Found 16-bit adder for signal <$n0007> created at line 62.
    Found 16-bit adder for signal <$n0008> created at line 63.
    Found 16-bit adder for signal <$n0009> created at line 65.
    Found 16-bit adder for signal <$n0010> created at line 66.
    Found 16-bit adder for signal <$n0011> created at line 67.
    Found 16-bit adder for signal <$n0012> created at line 68.
    Found 16-bit adder for signal <$n0013> created at line 69.
    Found 16-bit adder for signal <$n0014> created at line 70.