_primary.vhd

基于FPGA的波束成型

library verilog;
use verilog.vl_types.all;
entity gw is
    port(
        mux2            : in     vl_logic_vector(15 downto 0);
        eer             : in     vl_logic_vector(15 downto 0);
        eei             : in     vl_logic_vector(15 downto 0);
        w0r             : in     vl_logic_vector(15 downto 0);
        w0i             : in     vl_logic_vector(15 downto 0);
        w1r             : in     vl_logic_vector(15 downto 0);
        w1i             : in     vl_logic_vector(15 downto 0);
        w2r             : in     vl_logic_vector(15 downto 0);
        w2i             : in     vl_logic_vector(15 downto 0);
        w3r             : in     vl_logic_vector(15 downto 0);
        w3i             : in     vl_logic_vector(15 downto 0);
        w4r             : in     vl_logic_vector(15 downto 0);
        w4i             : in     vl_logic_vector(15 downto 0);
        w5r             : in     vl_logic_vector(15 downto 0);
        w5i             : in     vl_logic_vector(15 downto 0);
        w6r             : in     vl_logic_vector(15 downto 0);
        w6i             : in     vl_logic_vector(15 downto 0);
        w7r             : in     vl_logic_vector(15 downto 0);
        w7i             : in     vl_logic_vector(15 downto 0);
        yx0r            : in     vl_logic_vector(15 downto 0);
        yx0i            : in     vl_logic_vector(15 downto 0);
        yx1r            : in     vl_logic_vector(15 downto 0);
        yx1i            : in     vl_logic_vector(15 downto 0);
        yx2r            : in     vl_logic_vector(15 downto 0);
        yx2i            : in     vl_logic_vector(15 downto 0);
        yx3r            : in     vl_logic_vector(15 downto 0);
        yx3i            : in     vl_logic_vector(15 downto 0);
        yx4r            : in     vl_logic_vector(15 downto 0);
        yx4i            : in     vl_logic_vector(15 downto 0);
        yx5r            : in     vl_logic_vector(15 downto 0);
        yx5i            : in     vl_logic_vector(15 downto 0);
        yx6r            : in     vl_logic_vector(15 downto 0);
        yx6i            : in     vl_logic_vector(15 downto 0);
        yx7r            : in     vl_logic_vector(15 downto 0);
        yx7i            : in     vl_logic_vector(15 downto 0);
        wn0r            : out    vl_logic_vector(15 downto 0);
        wn0i            : out    vl_logic_vector(15 downto 0);
        wn1r            : out    vl_logic_vector(15 downto 0);
        wn1i            : out    vl_logic_vector(15 downto 0);
        wn2r            : out    vl_logic_vector(15 downto 0);
        wn2i            : out    vl_logic_vector(15 downto 0);
        wn3r            : out    vl_logic_vector(15 downto 0);
        wn3i            : out    vl_logic_vector(15 downto 0);
        wn4r            : out    vl_logic_vector(15 downto 0);
        wn4i            : out    vl_logic_vector(15 downto 0);
        wn5r            : out    vl_logic_vector(15 downto 0);
        wn5i            : out    vl_logic_vector(15 downto 0);
        wn6r            : out    vl_logic_vector(15 downto 0);
        wn6i            : out    vl_logic_vector(15 downto 0);
        wn7r            : out    vl_logic_vector(15 downto 0);
        wn7i            : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end gw;