_primary.vhd

基于FPGA的波束成型

library verilog;
use verilog.vl_types.all;
entity gyk is
    port(
        w0r             : in     vl_logic_vector(15 downto 0);
        w0i             : in     vl_logic_vector(15 downto 0);
        w1r             : in     vl_logic_vector(15 downto 0);
        w1i             : in     vl_logic_vector(15 downto 0);
        w2r             : in     vl_logic_vector(15 downto 0);
        w2i             : in     vl_logic_vector(15 downto 0);
        w3r             : in     vl_logic_vector(15 downto 0);
        w3i             : in     vl_logic_vector(15 downto 0);
        w4r             : in     vl_logic_vector(15 downto 0);
        w4i             : in     vl_logic_vector(15 downto 0);
        w5r             : in     vl_logic_vector(15 downto 0);
        w5i             : in     vl_logic_vector(15 downto 0);
        w6r             : in     vl_logic_vector(15 downto 0);
        w6i             : in     vl_logic_vector(15 downto 0);
        w7r             : in     vl_logic_vector(15 downto 0);
        w7i             : in     vl_logic_vector(15 downto 0);
        yx0r            : in     vl_logic_vector(15 downto 0);
        yx0i            : in     vl_logic_vector(15 downto 0);
        yx1r            : in     vl_logic_vector(15 downto 0);
        yx1i            : in     vl_logic_vector(15 downto 0);
        yx2r            : in     vl_logic_vector(15 downto 0);
        yx2i            : in     vl_logic_vector(15 downto 0);
        yx3r            : in     vl_logic_vector(15 downto 0);
        yx3i            : in     vl_logic_vector(15 downto 0);
        yx4r            : in     vl_logic_vector(15 downto 0);
        yx4i            : in     vl_logic_vector(15 downto 0);
        yx5r            : in     vl_logic_vector(15 downto 0);
        yx5i            : in     vl_logic_vector(15 downto 0);
        yx6r            : in     vl_logic_vector(15 downto 0);
        yx6i            : in     vl_logic_vector(15 downto 0);
        yx7r            : in     vl_logic_vector(15 downto 0);
        yx7i            : in     vl_logic_vector(15 downto 0);
        ykr             : out    vl_logic_vector(15 downto 0);
        yki             : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end gyk;