chwr.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    21:20:42 06/03/07
// Design Name:    
// Module Name:    chwr
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//选择Wopt	CLK为15倍基准时钟(或为gwt的输出rdy)
// 
////////////////////////////////////////////////////////////////////////////////
module chwr(aw0r,aw0i,aw1r,aw1i,aw2r,aw2i,aw3r,aw3i,aw4r,aw4i,aw5r,aw5i,aw6r,aw6i,aw7r,aw7i,
				w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
				wp0r,wp0i,wp1r,wp1i,wp2r,wp2i,wp3r,wp3i,wp4r,wp4i,wp5r,wp5i,wp6r,wp6i,wp7r,wp7i,clk,rdy1,rdy2);

input[15:0]	aw0r,aw0i,aw1r,aw1i,aw2r,aw2i,aw3r,aw3i,aw4r,aw4i,aw5r,aw5i,aw6r,aw6i,aw7r,aw7i;
input clk;
output[15:0] w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i;
output[15:0] wp0r,wp0i,wp1r,wp1i,wp2r,wp2i,wp3r,wp3i,wp4r,wp4i,wp5r,wp5i,wp6r,wp6i,wp7r,wp7i;//输出最终结果
output rdy1,rdy2;

reg[15:0] w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i;
reg[15:0] wp0r,wp0i,wp1r,wp1i,wp2r,wp2i,wp3r,wp3i,wp4r,wp4i,wp5r,wp5i,wp6r,wp6i,wp7r,wp7i;
reg rdy1,rdy2;
reg[9:0] count=0;


initial
	begin
				w0r<=16'b0;
				w0i<=16'b0;
				w1r<=16'b0;
				w1i<=16'b0;
				w2r<=16'b0;
				w2i<=16'b0;
				w3r<=16'b0;
				w3i<=16'b0;
				w4r<=16'b0;
				w4i<=16'b0;
				w5r<=16'b0;
				w5i<=16'b0;
				w6r<=16'b0;
				w6i<=16'b0;
				w7r<=16'b0;
				w7i<=16'b0;

				rdy2<=0;
				rdy1<=1;
	end

always @ (posedge clk)
	begin
		 count<=count+1;
		 if(count==1)
		 	begin
				w0r<=16'b0;
				w0i<=16'b0;
				w1r<=16'b0;
				w1i<=16'b0;
				w2r<=16'b0;
				w2i<=16'b0;
				w3r<=16'b0;
				w3i<=16'b0;
				w4r<=16'b0;
				w4i<=16'b0;
				w5r<=16'b0;
				w5i<=16'b0;
				w6r<=16'b0;
				w6i<=16'b0;
				w7r<=16'b0;
				w7i<=16'b0;

				rdy2<=0;
				rdy1<=1;
			end

		 else if(count<=500)
		 	begin
				w0r<=aw0r;
				w0i<=aw0i;
				w1r<=aw1r;
				w1i<=aw1i;
				w2r<=aw2r;
				w2i<=aw2i;
				w3r<=aw3r;
				w3i<=aw3i;
				w4r<=aw4r;
				w4i<=aw4i;
				w5r<=aw5r;
				w5i<=aw5i;
				w6r<=aw6r;
				w6i<=aw6i;
				w7r<=aw7r;
				w7i<=aw7i;

				wp0r<=16'b0;
				wp0i<=16'b0;
				wp2r<=16'b0;
				wp2i<=16'b0;
				wp1r<=16'b0;
				wp1i<=16'b0;
				wp3r<=16'b0;
				wp3i<=16'b0;
				wp4r<=16'b0;
				wp4i<=16'b0;
				wp5r<=16'b0;
				wp5i<=16'b0;
				wp6r<=16'b0;
				wp6i<=16'b0;
				wp7r<=16'b0;
				wp7i<=16'b0;

				rdy2<=0;
				rdy1<=1;

			end
		else
			begin

				wp0r<=aw0r;
				wp0i<=aw0i;
				wp1r<=aw1r;
				wp1i<=aw1i;
				wp2r<=aw2r;
				wp2i<=aw2i;
				wp3r<=aw3r;
				wp3i<=aw3i;
				wp4r<=aw4r;
				wp4i<=aw4i;
				wp5r<=aw5r;
				wp5i<=aw5i;
				wp6r<=aw6r;
				wp6i<=aw6i;
				wp7r<=aw7r;
				wp7i<=aw7i;

				w0r<=16'b0;
				w0i<=16'b0;
				w1r<=16'b0;
				w1i<=16'b0;
				w2r<=16'b0;
				w2i<=16'b0;
				w3r<=16'b0;
				w3i<=16'b0;
				w4r<=16'b0;
				w4i<=16'b0;
				w5r<=16'b0;
				w5i<=16'b0;
				w6r<=16'b0;
				w6i<=16'b0;
				w7r<=16'b0;
				w7i<=16'b0;

				rdy2<=1;
				rdy1<=0;
			end
	end




endmodule