📄 gwtwave.tfw
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1.03i
// \ \ Application : ISE Foundation
// / / Filename : gwtwave.tfw
// /___/ /\ Timestamp : Sun Jun 03 20:11:51 2007
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name: gwtwave
//Device: Xilinx
//
`timescale 1ns/1ps
module gwtwave;
reg [15:0] mux2 = 16'b0000000000000000;
reg [15:0] der = 16'b0000000000000000;
reg [15:0] dei = 16'b0000000000000000;
reg [15:0] w0r = 16'b0000000000000000;
reg [15:0] w0i = 16'b0000000000000000;
reg [15:0] w1r = 16'b0000000000000000;
reg [15:0] w1i = 16'b0000000000000000;
reg [15:0] w2r = 16'b0000000000000000;
reg [15:0] w2i = 16'b0000000000000000;
reg [15:0] w3r = 16'b0000000000000000;
reg [15:0] w3i = 16'b0000000000000000;
reg [15:0] w4r = 16'b0000000000000000;
reg [15:0] w4i = 16'b0000000000000000;
reg [15:0] w5r = 16'b0000000000000000;
reg [15:0] w5i = 16'b0000000000000000;
reg [15:0] w6r = 16'b0000000000000000;
reg [15:0] w6i = 16'b0000000000000000;
reg [15:0] w7r = 16'b0000000000000000;
reg [15:0] w7i = 16'b0000000000000000;
reg [15:0] yx0r = 16'b0000000000000000;
reg [15:0] yx0i = 16'b0000000000000000;
reg [15:0] yx1r = 16'b0000000000000000;
reg [15:0] yx1i = 16'b0000000000000000;
reg [15:0] yx2r = 16'b0000000000000000;
reg [15:0] yx2i = 16'b0000000000000000;
reg [15:0] yx3r = 16'b0000000000000000;
reg [15:0] yx3i = 16'b0000000000000000;
reg [15:0] yx4r = 16'b0000000000000000;
reg [15:0] yx4i = 16'b0000000000000000;
reg [15:0] yx5r = 16'b0000000000000000;
reg [15:0] yx5i = 16'b0000000000000000;
reg [15:0] yx6r = 16'b0000000000000000;
reg [15:0] yx6i = 16'b0000000000000000;
reg [15:0] yx7r = 16'b0000000000000000;
reg [15:0] yx7i = 16'b0000000000000000;
wire [15:0] wout0r;
wire [15:0] wout0i;
wire [15:0] wout1r;
wire [15:0] wout1i;
wire [15:0] wout2r;
wire [15:0] wout2i;
wire [15:0] wout3r;
wire [15:0] wout3i;
wire [15:0] wout4r;
wire [15:0] wout4i;
wire [15:0] wout5r;
wire [15:0] wout5i;
wire [15:0] wout6r;
wire [15:0] wout6i;
wire [15:0] wout7r;
wire [15:0] wout7i;
reg clk = 1'b0;
reg start = 1'b0;
wire rdy;
parameter PERIOD = 200;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
gwt UUT (
.mux2(mux2),
.der(der),
.dei(dei),
.w0r(w0r),
.w0i(w0i),
.w1r(w1r),
.w1i(w1i),
.w2r(w2r),
.w2i(w2i),
.w3r(w3r),
.w3i(w3i),
.w4r(w4r),
.w4i(w4i),
.w5r(w5r),
.w5i(w5i),
.w6r(w6r),
.w6i(w6i),
.w7r(w7r),
.w7i(w7i),
.yx0r(yx0r),
.yx0i(yx0i),
.yx1r(yx1r),
.yx1i(yx1i),
.yx2r(yx2r),
.yx2i(yx2i),
.yx3r(yx3r),
.yx3i(yx3i),
.yx4r(yx4r),
.yx4i(yx4i),
.yx5r(yx5r),
.yx5i(yx5i),
.yx6r(yx6r),
.yx6i(yx6i),
.yx7r(yx7r),
.yx7i(yx7i),
.wout0r(wout0r),
.wout0i(wout0i),
.wout1r(wout1r),
.wout1i(wout1i),
.wout2r(wout2r),
.wout2i(wout2i),
.wout3r(wout3r),
.wout3i(wout3i),
.wout4r(wout4r),
.wout4i(wout4i),
.wout5r(wout5r),
.wout5i(wout5i),
.wout6r(wout6r),
.wout6i(wout6i),
.wout7r(wout7r),
.wout7i(wout7i),
.clk(clk),
.start(start),
.rdy(rdy));
integer TX_ERROR = 0;
initial begin // Open the results file...
#10200 // Final time: 10200 ns
if (TX_ERROR == 0) begin
$display("No errors or warnings.");
end else begin
$display("%d errors found in simulation.", TX_ERROR);
end
$stop;
end
initial begin
// ------------- Current Time: 85ns
#85;
mux2 = 16'b0000000000001000;
der = 16'b0011000000011110;
w0r = 16'b0000000010010111;
w0i = 16'b1111111111100101;
w3r = 16'b1111111110010110;
w3i = 16'b1111111110110000;
// -------------------------------------
// ------------- Current Time: 285ns
#200;
dei = 16'b0000111110100010;
w1r = 16'b0000000000111110;
w1i = 16'b0000000000001111;
w2r = 16'b1111111111100100;
w2i = 16'b1111111111111011;
w4r = 16'b1111111110001001;
w4i = 16'b1111111110001000;
w5r = 16'b1111111111110111;
w5i = 16'b1111111110101100;
w6r = 16'b0000000000011100;
w6i = 16'b0000000000100001;
w7r = 16'b1111111111101110;
w7i = 16'b0000000010000001;
yx0r = 16'b0110001111101110;
yx0i = 16'b0010000011100011;
yx1r = 16'b0011110001100110;
yx1i = 16'b0010110100010111;
yx2r = 16'b1111101010011011;
yx2i = 16'b1111101101010001;
yx3r = 16'b1110011000000011;
yx3i = 16'b1011111101001110;
yx4r = 16'b1110010110000001;
yx4i = 16'b1001101101101111;
yx5r = 16'b0001110011010000;
yx5i = 16'b1100111010010001;
yx6r = 16'b1111100110100011;
yx6i = 16'b0001110111011001;
yx7r = 16'b1101001011101000;
yx7i = 16'b0011011000110000;
// -------------------------------------
// ------------- Current Time: 685ns
#400;
start = 1'b1;
// -------------------------------------
end
task CHECK_wout0r;
input [15:0] NEXT_wout0r;
#0 begin
if (NEXT_wout0r !== wout0r) begin
$display("Error at time=%dns wout0r=%b, expected=%b", $time, wout0r, NEXT_wout0r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout0i;
input [15:0] NEXT_wout0i;
#0 begin
if (NEXT_wout0i !== wout0i) begin
$display("Error at time=%dns wout0i=%b, expected=%b", $time, wout0i, NEXT_wout0i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout1r;
input [15:0] NEXT_wout1r;
#0 begin
if (NEXT_wout1r !== wout1r) begin
$display("Error at time=%dns wout1r=%b, expected=%b", $time, wout1r, NEXT_wout1r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout1i;
input [15:0] NEXT_wout1i;
#0 begin
if (NEXT_wout1i !== wout1i) begin
$display("Error at time=%dns wout1i=%b, expected=%b", $time, wout1i, NEXT_wout1i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout2r;
input [15:0] NEXT_wout2r;
#0 begin
if (NEXT_wout2r !== wout2r) begin
$display("Error at time=%dns wout2r=%b, expected=%b", $time, wout2r, NEXT_wout2r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout2i;
input [15:0] NEXT_wout2i;
#0 begin
if (NEXT_wout2i !== wout2i) begin
$display("Error at time=%dns wout2i=%b, expected=%b", $time, wout2i, NEXT_wout2i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout3r;
input [15:0] NEXT_wout3r;
#0 begin
if (NEXT_wout3r !== wout3r) begin
$display("Error at time=%dns wout3r=%b, expected=%b", $time, wout3r, NEXT_wout3r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout3i;
input [15:0] NEXT_wout3i;
#0 begin
if (NEXT_wout3i !== wout3i) begin
$display("Error at time=%dns wout3i=%b, expected=%b", $time, wout3i, NEXT_wout3i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout4r;
input [15:0] NEXT_wout4r;
#0 begin
if (NEXT_wout4r !== wout4r) begin
$display("Error at time=%dns wout4r=%b, expected=%b", $time, wout4r, NEXT_wout4r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout4i;
input [15:0] NEXT_wout4i;
#0 begin
if (NEXT_wout4i !== wout4i) begin
$display("Error at time=%dns wout4i=%b, expected=%b", $time, wout4i, NEXT_wout4i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout5r;
input [15:0] NEXT_wout5r;
#0 begin
if (NEXT_wout5r !== wout5r) begin
$display("Error at time=%dns wout5r=%b, expected=%b", $time, wout5r, NEXT_wout5r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout5i;
input [15:0] NEXT_wout5i;
#0 begin
if (NEXT_wout5i !== wout5i) begin
$display("Error at time=%dns wout5i=%b, expected=%b", $time, wout5i, NEXT_wout5i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout6r;
input [15:0] NEXT_wout6r;
#0 begin
if (NEXT_wout6r !== wout6r) begin
$display("Error at time=%dns wout6r=%b, expected=%b", $time, wout6r, NEXT_wout6r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout6i;
input [15:0] NEXT_wout6i;
#0 begin
if (NEXT_wout6i !== wout6i) begin
$display("Error at time=%dns wout6i=%b, expected=%b", $time, wout6i, NEXT_wout6i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout7r;
input [15:0] NEXT_wout7r;
#0 begin
if (NEXT_wout7r !== wout7r) begin
$display("Error at time=%dns wout7r=%b, expected=%b", $time, wout7r, NEXT_wout7r);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_wout7i;
input [15:0] NEXT_wout7i;
#0 begin
if (NEXT_wout7i !== wout7i) begin
$display("Error at time=%dns wout7i=%b, expected=%b", $time, wout7i, NEXT_wout7i);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
task CHECK_rdy;
input NEXT_rdy;
#0 begin
if (NEXT_rdy !== rdy) begin
$display("Error at time=%dns rdy=%b, expected=%b", $time, rdy, NEXT_rdy);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
endmodule
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