addm.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    11:56:14 06/04/07
// Design Name:    
// Module Name:    addm
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module addm(war1,war2,war3,war4,war5,war6,war7,war8,wai1,wai2,wai3,wai4,wai5,wai6,wai7,wai8,
				yar,yai,clk,start,rdy);

input[31:0] war1,war2,war3,war4,war5,war6,war7,war8,wai1,wai2,wai3,wai4,wai5,wai6,wai7,wai8;
input clk,start;
output[31:0] yar,yai;
output rdy;

reg[31:0] wbr1,wbr2,wbr4,wbr3,wbi1,wbi2,wbi4,wbi3,yai,yar;
reg[31:0] wcr1,wcr2,wci1,wci2;
reg rdy=0;

always @ (posedge clk)
	begin
		if(start)
			begin
				wbr1<=war1+war2;
				wbr2<=war3+war4;
				wbr3<=war5+war6;
				wbr4<=war7+war8;

				wcr1<=wbr1+wbr2;
				wcr2<=wbr3+wbr4;

				//输出结果（实数部分）
				//yr<=wcr1+wcr2;
				

				//虚数运算
				wbi1<=wai1+wai2;
				wbi2<=wai3+wai4;
				wbi3<=wai5+wai6;
				wbi4<=wai7+wai8;

				wci1<=wbi1+wbi2;
				wci2<=wbi3+wbi4;

				//输出结果（虚数部分）
				//yi<=wci1+wci2;	
				//rdy<=1;
			end
			else 
				begin
					wcr1<=32'b0;
					wcr2<=32'b0;
					wci1<=32'b0;
					wci2<=32'b0;
				end
	end

	always @ (wcr1 or wcr2 or wci1 or wci2)

		begin
			
			//输出结果（虚数部分）
			yai<=wci1+wci2;

			//输出结果（实数部分）
			yar<=wcr1+wcr2;
			rdy<=1;
		end



endmodule