boshuxc.syr

来自「基于FPGA的波束成型」· SYR 代码 · 共 525 行 · 第 1/2 页

Register <mu1/u2/ain_0> equivalent to <mu1/u4/ain_0> has been removed
Register <mu1/u1/bin_0> equivalent to <mu1/u4/bin_0> has been removed
Register <mu1/u1/ain_0> equivalent to <mu1/u3/ain_0> has been removed
Register <mu1/u2/bin_0> equivalent to <mu1/u3/bin_0> has been removed
Register <mu2/u2/ain_0> equivalent to <mu2/u4/ain_0> has been removed
Register <mu2/u1/bin_0> equivalent to <mu2/u4/bin_0> has been removed
Register <mu2/u1/ain_0> equivalent to <mu2/u3/ain_0> has been removed
Register <mu2/u2/bin_0> equivalent to <mu2/u3/bin_0> has been removed
Register <mu3/u2/ain_0> equivalent to <mu3/u4/ain_0> has been removed
Register <mu3/u1/bin_0> equivalent to <mu3/u4/bin_0> has been removed
Register <mu3/u1/ain_0> equivalent to <mu3/u3/ain_0> has been removed
Register <mu3/u2/bin_0> equivalent to <mu3/u3/bin_0> has been removed
Register <mu4/u2/ain_0> equivalent to <mu4/u4/ain_0> has been removed
Register <mu4/u1/bin_0> equivalent to <mu4/u4/bin_0> has been removed
Register <mu4/u1/ain_0> equivalent to <mu4/u3/ain_0> has been removed
Register <mu4/u2/bin_0> equivalent to <mu4/u3/bin_0> has been removed
Register <mu5/u2/ain_0> equivalent to <mu5/u4/ain_0> has been removed
Register <mu5/u1/bin_0> equivalent to <mu5/u4/bin_0> has been removed
Register <mu5/u1/ain_0> equivalent to <mu5/u3/ain_0> has been removed
Register <mu5/u2/bin_0> equivalent to <mu5/u3/bin_0> has been removed
Register <mu6/u2/ain_0> equivalent to <mu6/u4/ain_0> has been removed
Register <mu6/u1/bin_0> equivalent to <mu6/u4/bin_0> has been removed
Register <mu6/u1/ain_0> equivalent to <mu6/u3/ain_0> has been removed
Register <mu6/u2/bin_0> equivalent to <mu6/u3/bin_0> has been removed
Register <mu7/u2/ain_0> equivalent to <mu7/u4/ain_0> has been removed
Register <mu7/u1/bin_0> equivalent to <mu7/u4/bin_0> has been removed
Register <mu7/u1/ain_0> equivalent to <mu7/u3/ain_0> has been removed
Register <mu7/u2/bin_0> equivalent to <mu7/u3/bin_0> has been removed
Register <mu8/u2/ain_0> equivalent to <mu8/u4/ain_0> has been removed
Register <mu8/u1/bin_0> equivalent to <mu8/u4/bin_0> has been removed
Register <mu8/u1/ain_0> equivalent to <mu8/u3/ain_0> has been removed
Register <mu8/u2/bin_0> equivalent to <mu8/u3/bin_0> has been removed
FlipFlop mu1/u4/rdy has been replicated 24 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : boshuxc.ngr
Top Level Output File Name         : boshuxc
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 579

Macro Statistics :
# Registers                        : 131
#      1-bit register              : 33
#      16-bit register             : 64
#      32-bit register             : 34
# Adders/Subtractors               : 134
#      16-bit adder                : 72
#      32-bit adder                : 54
#      32-bit subtractor           : 8
# Multipliers                      : 32
#      16x16-bit registered multiplier: 32

Cell Usage :
# BELS                             : 11633
#      BUF                         : 2
#      GND                         : 1
#      INV                         : 2075
#      LUT1                        : 104
#      LUT2                        : 344
#      LUT2_D                      : 4
#      LUT2_L                      : 720
#      LUT3                        : 927
#      LUT3_D                      : 2
#      LUT3_L                      : 264
#      LUT4                        : 1117
#      LUT4_D                      : 6
#      LUT4_L                      : 54
#      MUXCY                       : 3002
#      VCC                         : 1
#      XORCY                       : 3010
# FlipFlops/Latches                : 2106
#      FDE                         : 992
#      FDR                         : 1114
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 578
#      IBUF                        : 513
#      OBUF                        : 65
# MULTs                            : 32
#      MULT18X18S                  : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                    3116  out of   3584    86%  
 Number of Slice Flip Flops:          2106  out of   7168    29%  
 Number of 4 input LUTs:              3542  out of   7168    49%  
 Number of bonded IOBs:                579  out of    141   410% (*) 
 Number of MULT18X18s:                  32  out of     16   200% (*) 
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 2138  |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.903ns (Maximum Frequency: 71.927MHz)
   Minimum input arrival time before clock: 8.794ns
   Maximum output required time after clock: 6.216ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 13.903ns (frequency: 71.927MHz)
  Total number of paths / destination ports: 53784431 / 2177
-------------------------------------------------------------------------
Delay:               13.903ns (Levels of Logic = 39)
  Source:            mu1/u3/out_0 (FF)
  Destination:       yi_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: mu1/u3/out_0 to yi_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  mu1/u3/out_0 (mu1/u3/out_0)
     LUT2_L:I0->LO         1   0.479   0.000  mu1/complexmul__n0001<0>lut (mu1/N4)
     MUXCY:S->O            1   0.435   0.000  mu1/complexmul__n0001<0>cy (mu1/complexmul__n0001<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<1>cy (mu1/complexmul__n0001<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<2>cy (mu1/complexmul__n0001<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<3>cy (mu1/complexmul__n0001<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<4>cy (mu1/complexmul__n0001<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<5>cy (mu1/complexmul__n0001<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<6>cy (mu1/complexmul__n0001<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<7>cy (mu1/complexmul__n0001<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<8>cy (mu1/complexmul__n0001<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<9>cy (mu1/complexmul__n0001<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<10>cy (mu1/complexmul__n0001<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<11>cy (mu1/complexmul__n0001<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<12>cy (mu1/complexmul__n0001<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<13>cy (mu1/complexmul__n0001<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<14>cy (mu1/complexmul__n0001<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<15>cy (mu1/complexmul__n0001<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<16>cy (mu1/complexmul__n0001<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<17>cy (mu1/complexmul__n0001<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<18>cy (mu1/complexmul__n0001<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<19>cy (mu1/complexmul__n0001<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<20>cy (mu1/complexmul__n0001<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<21>cy (mu1/complexmul__n0001<21>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<22>cy (mu1/complexmul__n0001<22>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<23>cy (mu1/complexmul__n0001<23>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<24>cy (mu1/complexmul__n0001<24>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<25>cy (mu1/complexmul__n0001<25>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mu1/complexmul__n0001<26>cy (mu1/complexmul__n0001<26>_cyo)
     XORCY:CI->O           2   0.786   0.915  mu1/complexmul__n0001<27>_xor (mu1/_n0001<27>)
     LUT2:I1->O            1   0.479   0.681  mu1/qi<27>1 (wai1<27>)
     MUXCY:DI->O           1   0.774   0.000  boshuxc_wbi1<27>cy (boshuxc_wbi1<27>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc_wbi1<28>cy (boshuxc_wbi1<28>_cyo)
     XORCY:CI->O           1   0.786   0.851  boshuxc_wbi1<29>_xor (wbi1<29>)
     LUT2_L:I1->LO         1   0.479   0.000  boshuxc_wci1<29>lut (N349)
     MUXCY:S->O            1   0.435   0.000  boshuxc_wci1<29>cy (boshuxc_wci1<29>_cyo)
     XORCY:CI->O           1   0.786   0.976  boshuxc_wci1<30>_xor (wci1<30>)
     LUT2_L:I0->LO         1   0.479   0.000  boshuxc__n0009<30>lut (N446)
     MUXCY:S->O            0   0.435   0.000  boshuxc__n0009<30>cy (boshuxc__n0009<30>_cyo)
     XORCY:CI->O           1   0.786   0.000  boshuxc__n0009<31>_xor (_n0009<31>)
     FDR:D                     0.176          yi_31
    ----------------------------------------
    Total                     13.903ns (9.440ns logic, 4.463ns route)
                                       (67.9% logic, 32.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 38153 / 4025
-------------------------------------------------------------------------
Offset:              8.794ns (Levels of Logic = 21)
  Source:            ai1<0> (PAD)
  Destination:       mu1/u4/ain_15 (FF)
  Destination Clock: clk rising

  Data Path: ai1<0> to mu1/u4/ain_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.715   1.074  ai1_0_IBUF (ai1_0_IBUF)
     LUT1:I0->O            1   0.479   0.000  ai1_0_IBUF_rt (ai1_0_IBUF_rt)
     MUXCY:S->O            1   0.435   0.000  boshuxc__n0000<0>cy (boshuxc__n0000<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<1>cy (boshuxc__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<2>cy (boshuxc__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<3>cy (boshuxc__n0000<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<4>cy (boshuxc__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<5>cy (boshuxc__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<6>cy (boshuxc__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<7>cy (boshuxc__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<8>cy (boshuxc__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<9>cy (boshuxc__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<10>cy (boshuxc__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<11>cy (boshuxc__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<12>cy (boshuxc__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  boshuxc__n0000<13>cy (boshuxc__n0000<13>_cyo)
     MUXCY:CI->O           0   0.056   0.000  boshuxc__n0000<14>cy (boshuxc__n0000<14>_cyo)
     XORCY:CI->O          94   0.786   1.877  boshuxc__n0000<15>_xor (_n0000<15>)
     INV:I->O              0   0.479   0.000  mu1/u4/_n0011<15>1_INV_0 (mu1/u4/_n0011<15>)
     XORCY:LI->O           1   0.541   0.976  mu1/u2/mult__n0004<15>_xor (mu1/u2/_n0004<15>)
     LUT2:I0->O            1   0.479   0.000  mu1/u2/_n0000<15>1 (mu1/u2/_n0000<15>)
     FDE:D                     0.176          mu1/u2/ain_15
    ----------------------------------------
    Total                      8.794ns (4.867ns logic, 3.927ns route)
                                       (55.3% logic, 44.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 65 / 65
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            rdy (FF)
  Destination:       rdy (PAD)
  Source Clock:      clk rising

  Data Path: rdy to rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.626   0.681  rdy (rdy_OBUF)
     OBUF:I->O                 4.909          rdy_OBUF (rdy)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
CPU : 118.20 / 119.53 s | Elapsed : 118.00 / 118.00 s
 
--> 

Total memory usage is 139524 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    0 (   0 filtered)