boshuwave.tfw

基于FPGA的波束成型

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.03i
//  \   \         Application : ISE Foundation
//  /   /         Filename : boshuwave.tfw
// /___/   /\     Timestamp : Mon Jun 04 15:44:53 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: boshuwave
//Device: Xilinx
//
`timescale 1ns/1ps

module boshuwave;
    reg [15:0] ar1 = 16'b0000000000000000;
    reg [15:0] ar2 = 16'b0000000000000000;
    reg [15:0] ar3 = 16'b0000000000000000;
    reg [15:0] ar4 = 16'b0000000000000000;
    reg [15:0] ar5 = 16'b0000000000000000;
    reg [15:0] ar6 = 16'b0000000000000000;
    reg [15:0] ar7 = 16'b0000000000000000;
    reg [15:0] ar8 = 16'b0000000000000000;
    reg [15:0] ai1 = 16'b0000000000000000;
    reg [15:0] ai2 = 16'b0000000000000000;
    reg [15:0] ai3 = 16'b0000000000000000;
    reg [15:0] ai4 = 16'b0000000000000000;
    reg [15:0] ai5 = 16'b0000000000000000;
    reg [15:0] ai6 = 16'b0000000000000000;
    reg [15:0] ai7 = 16'b0000000000000000;
    reg [15:0] ai8 = 16'b0000000000000000;
    reg [15:0] br1 = 16'b0000000000000000;
    reg [15:0] br2 = 16'b0000000000000000;
    reg [15:0] br3 = 16'b0000000000000000;
    reg [15:0] br4 = 16'b0000000000000000;
    reg [15:0] br5 = 16'b0000000000000000;
    reg [15:0] br6 = 16'b0000000000000000;
    reg [15:0] br7 = 16'b0000000000000000;
    reg [15:0] br8 = 16'b0000000000000000;
    reg [15:0] bi1 = 16'b0000000000000000;
    reg [15:0] bi2 = 16'b0000000000000000;
    reg [15:0] bi3 = 16'b0000000000000000;
    reg [15:0] bi4 = 16'b0000000000000000;
    reg [15:0] bi5 = 16'b0000000000000000;
    reg [15:0] bi6 = 16'b0000000000000000;
    reg [15:0] bi7 = 16'b0000000000000000;
    reg [15:0] bi8 = 16'b0000000000000000;
    wire [31:0] yr;
    wire [31:0] yi;
    reg clk = 1'b0;
    reg start = 1'b0;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    boshuxc UUT (
        .ar1(ar1),
        .ar2(ar2),
        .ar3(ar3),
        .ar4(ar4),
        .ar5(ar5),
        .ar6(ar6),
        .ar7(ar7),
        .ar8(ar8),
        .ai1(ai1),
        .ai2(ai2),
        .ai3(ai3),
        .ai4(ai4),
        .ai5(ai5),
        .ai6(ai6),
        .ai7(ai7),
        .ai8(ai8),
        .br1(br1),
        .br2(br2),
        .br3(br3),
        .br4(br4),
        .br5(br5),
        .br6(br6),
        .br7(br7),
        .br8(br8),
        .bi1(bi1),
        .bi2(bi2),
        .bi3(bi3),
        .bi4(bi4),
        .bi5(bi5),
        .bi6(bi6),
        .bi7(bi7),
        .bi8(bi8),
        .yr(yr),
        .yi(yi),
        .clk(clk),
        .start(start));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin  // Open the results file...
        TX_FILE = $fopen("results.txt");
        #10200 // Final time:  10200 ns
        if (TX_ERROR == 0) begin
            $display("No errors or warnings.");
            $fdisplay(TX_FILE, "No errors or warnings.");
        end else begin
            $display("%d errors found in simulation.", TX_ERROR);
            $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
        end
        $fclose(TX_FILE);
        $stop;
    end

    initial begin
        // -------------  Current Time:  285ns
        #285;
        ai1 = 16'b0000000000100011;
        ai2 = 16'b0000001000100110;
        ai3 = 16'b0000000101010110;
        ai4 = 16'b1111111110101010;
        ai5 = 16'b1111111001111000;
        ai6 = 16'b1111111010001110;
        ai7 = 16'b0000000000110011;
        ai8 = 16'b0000000111000111;
        ar1 = 16'b0000000111010100;
        ar2 = 16'b0000000011010111;
        ar3 = 16'b1111111011101001;
        ar4 = 16'b1111111000101010;
        ar5 = 16'b1111111100101001;
        ar6 = 16'b0000000101100100;
        ar7 = 16'b0000000111011110;
        ar8 = 16'b0000000010000111;
        bi1 = 16'b0010000011100011;
        bi2 = 16'b0010110100010111;
        bi3 = 16'b1111101101010001;
        bi4 = 16'b1011111101001110;
        bi5 = 16'b1001101101101111;
        bi6 = 16'b1100111010010001;
        bi7 = 16'b0001110111011001;
        bi8 = 16'b0011011000110000;
        br1 = 16'b0110001111101110;
        br2 = 16'b0011110001100110;
        br3 = 16'b1111101010011011;
        br4 = 16'b1110011000000011;
        br5 = 16'b1110010110000001;
        br6 = 16'b0001110011010000;
        br7 = 16'b1111100110100011;
        br8 = 16'b1101001011101000;
        // -------------------------------------
        // -------------  Current Time:  685ns
        #400;
        start = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  1485ns
        #800;
        bi1 = 16'b0100010101110100;
        bi2 = 16'b0100110100010001;
        bi3 = 16'b0001100101001111;
        bi4 = 16'b1100101110100110;
        bi5 = 16'b1010011110011010;
        bi6 = 16'b1011010001000001;
        bi7 = 16'b1110101010110011;
        bi8 = 16'b0001111001101100;
        br1 = 16'b0101001010110101;
        br2 = 16'b0010100010101000;
        br3 = 16'b0000000110101111;
        br4 = 16'b1111011100100011;
        br5 = 16'b0001111010001111;
        br6 = 16'b0001011011000000;
        br7 = 16'b0000100011001011;
        br8 = 16'b1101001011001111;
        // -------------------------------------
    end

    task CHECK_yr;
        input [31:0] NEXT_yr;

        #0 begin
            if (NEXT_yr !== yr) begin
                $display("Error at time=%dns yr=%b, expected=%b", $time, yr, NEXT_yr);
                $fdisplay(TX_FILE, "Error at time=%dns yr=%b, expected=%b", $time, yr, NEXT_yr);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_yi;
        input [31:0] NEXT_yi;

        #0 begin
            if (NEXT_yi !== yi) begin
                $display("Error at time=%dns yi=%b, expected=%b", $time, yi, NEXT_yi);
                $fdisplay(TX_FILE, "Error at time=%dns yi=%b, expected=%b", $time, yi, NEXT_yi);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask

endmodule