_primary.vhd

基于FPGA的波束成型

library verilog;
use verilog.vl_types.all;
entity addm is
    port(
        war1            : in     vl_logic_vector(31 downto 0);
        war2            : in     vl_logic_vector(31 downto 0);
        war3            : in     vl_logic_vector(31 downto 0);
        war4            : in     vl_logic_vector(31 downto 0);
        war5            : in     vl_logic_vector(31 downto 0);
        war6            : in     vl_logic_vector(31 downto 0);
        war7            : in     vl_logic_vector(31 downto 0);
        war8            : in     vl_logic_vector(31 downto 0);
        wai1            : in     vl_logic_vector(31 downto 0);
        wai2            : in     vl_logic_vector(31 downto 0);
        wai3            : in     vl_logic_vector(31 downto 0);
        wai4            : in     vl_logic_vector(31 downto 0);
        wai5            : in     vl_logic_vector(31 downto 0);
        wai6            : in     vl_logic_vector(31 downto 0);
        wai7            : in     vl_logic_vector(31 downto 0);
        wai8            : in     vl_logic_vector(31 downto 0);
        yar             : out    vl_logic_vector(31 downto 0);
        yai             : out    vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end addm;