start.s

picoos源码。The RTOS and the TCP/IP stack will be built automatically.

..inst_prot_spin:
    b       ..inst_prot_spin
..inst_prot_string:
    .4byte 0x0d0a0d0a
    .byte "Unexpected Instruction storage protection violation detected"
    .byte  0x0d,0x0a,0x00,0x00

    /* External interrupt */
    .align 2
..External_vector:
    addis   r3, 0,..inst_ext_string@h
    ori     r3,r3,..inst_ext_string@l
    bl      u_print
..inst_ext_spin:
    b       ..inst_ext_spin
..inst_ext_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected external interrupt occurred"
    .byte   0x0d,0x0a,0x00,0x00,0x00,0x00

    /* Alignment exception */
    .align 2
..Alignment_vector:
    addis   r3, 0,..algn_string@h
    ori     r3,r3,..algn_string@l
    bl      u_print
..algn_spin:
    b       ..algn_spin
..algn_string:
    .4byte  0x0d0a0d0a
    .byte   "Alignment exception detected"
    .byte   0x0d,0x0a,0x00,0x00

    /* FPU exception */
    .align 2
..FPU_vector:
    addis   r3, 0,..fpu_string@h
    ori     r3,r3,..fpu_string@l
    bl      u_print
..fpu_spin:
    b       ..fpu_spin
..fpu_string:
    .4byte  0x0d0a0d0a
    .byte   "FPU exception detected"
    .byte   0x0d,0x0a,0x00,0x00,0x00,0x00

    /* Program exception */
    .align 2
..Program_vector:
    addis   r3, 0,..prog_string@h
    ori     r3,r3,..prog_string@l
    bl      u_print
..prog_spin:
    b       ..prog_spin
..prog_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Program exception detected"
    .byte   0x0d,0x0a,0x00

    /* System call */
    .align 2
..Sys_call_vector:
    addis   r3, 0,..sysc_string@h
    ori     r3,r3,..sysc_string@l
    bl      u_print
..sysc_spin:
    b       ..sysc_spin
..sysc_string:
    .4byte  0x0d0a0d0a
    .byte   "System call detected"
    .byte   0x0d,0x0a,0x00,0x00

    /* Auxiliary Processor Unavailable */
    .align 2
..AUX_vector:
    addis   r3, 0,..aux_string@h
    ori     r3,r3,..aux_string@l
    bl      u_print
..aux_spin:
    b       ..aux_spin
..aux_string:
    .4byte  0x0d0a0d0a
    .byte   "auxiliary processor unavailable detected"
    .byte   0x0d,0x0a,0x00,0x00

    /* Programmable interval timer */
    .align 2
..Pg_timer_vector:
    addis   r3, 0,..inst_timer_string@h
    ori     r3,r3,..inst_timer_string@l
    bl      u_print
..inst_timer_spin:
    b       ..inst_timer_spin
..inst_timer_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected timer interrupt occurred"
    .byte   0x0d,0x0a,0x00,0x00,0x00

    /* Fixed interval timer exception */
    .align 2
..Fx_timer_vector:
    addis   r3, 0,..fint_string@h
    ori     r3,r3,..fint_string@l 
    bl      u_print
..fint_spin:
    b       ..fint_spin
..fint_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Fixed interval timer expiration detected"
    .byte   0x0d,0x0a,0x00,0x00,0x00

    /* Watchdog timer exception */
    .align 2
..Watchdog_vector:
    addis   r3, 0,..wchd_string@h 
    ori     r3,r3,..wchd_string@l          
    bl      u_print
..wchd_spin:
    b       ..wchd_spin
..wchd_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Watchdog timer expiration detected"
    .byte   0x0d,0x0a,0x00

    /* Data TLB Miss exception */
    .align 2
..Data_TLB_miss_vector:
    addis   r3, 0,..dtlb_string@h
    ori     r3,r3,..dtlb_string@l
    bl      u_print
..dtlb_spin:
    b       ..dtlb_spin
..dtlb_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Data TLB Miss detected"
    .byte   0x0d,0x0a,0x00

    /* Instruction TLB Miss exception */
    .align 2
..Inst_TLB_miss_vector:
    addis   r3, 0,..itlb_string@h
    ori     r3,r3,..itlb_string@l
    bl      u_print
..itlb_spin:
    b       ..itlb_spin
..itlb_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Instruction TLB Miss detected"
    .byte   0x0d,0x0a,0x00,0x00

    /* Debug exception */
    .align 2
..Debug_vector:
    addis   r3, 0,..debg_string@h 
    ori     r3,r3,..debg_string@l          
    bl      u_print
..debg_spin:
    b       ..debg_spin
..debg_string:
    .4byte  0x0d0a0d0a
    .byte   "Unexpected Debug exception detected"
    .byte   0x0d,0x0a,0x00,0x00,0x00


        .align 2
..jumpover:

    /*  Initialize interrupt vector jump table */
    xor     r0,r0,r0   
    mtspr   IVPR,r0
    ori     r4,r0,..crit_vector
    mtspr   IVOR0,r4
    ori     r4,r0,..mach_vector
    mtspr   IVOR1,r4
    ori     r4,r0,..prot_vector
    mtspr   IVOR2,r4
    ori     r4,r0,..isi_vector
    mtspr   IVOR3,r4
    ori     r4,r0,..ext_vector
    mtspr   IVOR4,r4
    ori     r4,r0,..align_vector
    mtspr   IVOR5,r4
    ori     r4,r0,..prog_vector
    mtspr   IVOR6,r4
    ori     r4,r0,..fpu_vector
    mtspr   IVOR7,r4
    ori     r4,r0,..sys_vector
    mtspr   IVOR8,r4
    ori     r4,r0,..apu_vector
    mtspr   IVOR9,r4
    ori     r4,r0,..dec_vector
    mtspr   IVOR10,r4
    ori     r4,r0,..fit_vector
    mtspr   IVOR11,r4
    ori     r4,r0,..wadt_vector
    mtspr   IVOR12,r4
    ori     r4,r0,..dtlb_vector
    mtspr   IVOR13,r4
    ori     r4,r0,..itlb_vector
    mtspr   IVOR14,r4
    ori     r4,r0,..debug_vector
    mtspr   IVOR15,r4

    mflr    r1   /* save link reg in r1 */
    bl      ..end_list
    .long   ..crit_vector
    ba      ..Critical_vector
    .long   ..mach_vector
    ba      ..Machine_check_vector
    .long   ..prot_vector
    ba      ..Data_protection_vector
    .long   ..isi_vector
    ba      ..Instruction_protection_vector
    .long   ..ext_vector
    /* ba      ..External_vector */
    ba      p_asm_extISR
    .long   ..align_vector
    ba      ..Alignment_vector
    .long   ..prog_vector
    ba      ..Program_vector
    .long   ..fpu_vector
    ba      ..FPU_vector
    .long   ..sys_vector
    ba      ..Sys_call_vector
    .long   ..apu_vector
    ba      ..AUX_vector
    .long   ..dec_vector
    /* ba      ..Pg_timer_vector */
    ba      p_asm_timerISR
    .long   ..fit_vector
    ba      ..Fx_timer_vector
    .long   ..wadt_vector
    ba      ..Watchdog_vector
    .long   ..dtlb_vector 
    ba      ..Data_TLB_miss_vector
    .long   ..itlb_vector
    ba      ..Inst_TLB_miss_vector
    .long   ..debug_vector 
    ba      ..Debug_vector
    .long 0
    .long 0
..end_list:
    mflr    r4
    addi    r4,r4,-8   /* adjust for loop load */
..vec_loop:
    lwzu    r5,8(r4)
    lwz     r6,4(r4)
    cmpw    0,r5,0
    beq     ..vec_done
    stw     r6,0(r5)    /* store branch */
    dcbf    r0,r5       /* flush to storage */
    b       ..vec_loop
..vec_done:
    isync
    mtlr    r1


    /* initialize CPC0_CR0
       (set ext. clock for UART0) */
    addis   r3, 0,CPC0_CR0_INIT@h
    ori     r3,r3,CPC0_CR0_INIT@l
    mtdcr   CPC0_CR0,r3

    /* initialize UART0 */
    addi    r3, 0,(UART_DIV_9600_LO+(UART_DIV_9600_HI<<8))
    addis   r7, 0,UART0_MMIO_BASE@h
    ori     r7,r7,UART0_MMIO_BASE@l
    addi    r4, 0,0x80                /* get access to baudrate registers */
    stb     r4,UART_LINE_CONTROL(r7)
    stb     r3,UART_DL_LSB(r7)
    rlwinm  r4,r3,24,0x000000FF
    stb     r4,UART_DL_MSB(r7)
    addi    r4, 0,0x03                /* lcr: 8 bits, no parity */
    stb     r4,UART_LINE_CONTROL(r7)
    addi    r4, 0,0x00                /* disable FIFO */
    stb     r4,UART_FIFO_CONTROL(r7)
    addi    r4, 0,0x03                /* modem control: DTR RTS */
    stb     r4,UART_MODEM_CONTROL(r7)
    lbz     r3,UART_LINE_STATUS(r7)   /* clear line status */
    lbz     r3,UART_DATA_REG(r7)      /* read receive buffer */
    addi    r4, 0,0x00                /* set interrupt enable reg */
    stb     r4,UART_INT_ENABLE(r7)

    /* clear timer registers */
    xor     r0,r0,r0  /* r0 = 0x00000000 */
    addi    r1, 0,-1  /* r1 = 0xFFFFFFFF */
    mtspr   DEC,r0
    mtspr   TBLW,r0
    mtspr   TBUW,r0
    mtspr   TSR,r1
    mtspr   TCR,r0

    /* reset interrupt controllers */
    mtdcr   UIC1_ER,r0
    mtdcr   UIC1_SR,r1
    mtdcr   UIC0_ER,r0
    mtdcr   UIC0_SR,r1

    /* clear misc registers */
    mtspr   ESR,r0
    mtspr   XER,r0

    /* initialize MSR */
    addis   r3, 0,MSR_VALUE@h
    ori     r3,r3,MSR_VALUE@l
    mtmsr   r3

    /* set up stackpointer, write zero stack frame */
    addis   r1, 0,__STACK_TOP@h
    ori     r1,r1,__STACK_TOP@l
    rlwinm  r1,r1, 0, 0xFFFFFFE0 /* align stack */
    addi    r3, 0,32/4
    mtctr   r3
..wzero:
    stwu    r0,-4(r1)
    bdnz    ..wzero

    /* jump to C init function */
    bl      c_start
..halt:
    b       ..halt



/*---------------------------------------------------------------------------
 |
 |  FUNCTION:
 |
 |    void u_print(char *str);
 |
 |    Terminal output to UART0:
 |      write a character string to the terminal
 |
 *-------------------------------------------------------------------------*/

    .align  2
u_print:
    mflr    r6
    addi    r7,r3,0
..uploop:
    lbz     r3,0x0(r7)   /* get next char   */
    cmpi    0,0,r3,0x00  /* end of string?  */
    beq     ..upend
    bl      u_putch      /* print character */
    addi    r7,r7,1
    b       ..uploop
..upend:
    mtlr    r6
    blr
    ENDFUNC(u_print)



/*---------------------------------------------------------------------------
 |
 |  FUNCTION:
 |
 |    void u_putch(char c);
 |
 |    Terminal output to UART0:
 |      write a character to the terminal
 |
 *-------------------------------------------------------------------------*/

    .align  2
u_putch:
    addis   r4, 0,UART0_MMIO_BASE@h
    ori     r4,r4,UART0_MMIO_BASE@l
    cmpi    0,0,r3,10  /* line feed? */
    bne     ..u_pwait2
    xor     r0,r0,r0
    ori     r0,r0,13
..u_pwait1:
    lbz     r5,UART_LINE_STATUS(r4)
    eieio
    andi.   r5,r5,0x20  /* test THRE bit */
    beq     ..u_pwait1
    stb     r0,UART_DATA_REG(r4)
    eieio
..u_pwait2:
    lbz     r5,UART_LINE_STATUS(r4)
    eieio
    andi.   r5,r5,0x20  /* test THRE bit */
    beq     ..u_pwait2
    stb     r3,UART_DATA_REG(r4)
    eieio
    blr
    ENDFUNC(u_putch)



/*---------------------------------------------------------------------------
 |
 |  FUNCTION:
 |
 |    int u_getch(void);
 |
 |    Terminal input from UART0:
 |      read a character from the terminal
 |
 *-------------------------------------------------------------------------*/

    .align  2
u_getch:
    addis   r4, 0,UART0_MMIO_BASE@h
    ori     r4,r4,UART0_MMIO_BASE@l
..u_gwait:
    lbz     r3,UART_LINE_STATUS(r4)
    eieio
    andi.   r3,r3,0x01  /* test DR bit */
    beq     ..u_gwait 
    lbz     r3,UART_DATA_REG(r4)
    blr
    ENDFUNC(u_getch)



/*---------------------------------------------------------------------------
 |
 |  FUNCTION:
 |
 |    int u_kbhit(void);
 |
 |    Terminal input from UART0:
 |      returns nonzero when a key was hit on the terminal
 |
 *-------------------------------------------------------------------------*/

    .align  2
u_kbhit:
    addis   r4, 0,UART0_MMIO_BASE@h
    ori     r4,r4,UART0_MMIO_BASE@l
    lbz     r3,UART_LINE_STATUS(r4)
    eieio
    andi.   r3,r3,0x01  /* get DR bit */
    blr
    ENDFUNC(u_kbhit)