idt70840.c.bak

IDT72v90823时隙交叉芯片的 的功能驱动代码

/* idt72v90823.c - IDT 72V90823 driver source */

/*
modification history
--------------------
*/

#include "idt72v70840.h"





void tsiInit()
{         
	  volatile char wait;
	  unsigned long int *POINT;
	  POINT = (unsigned long int *) (CS_TSI70840+FAR);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR0);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR1);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR2);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR3);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR4);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR5);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR6);
	  *POINT = 0x0000;
	  POINT = (unsigned long int *) (CS_TSI70840+OR7);
	  *POINT = 0x0000;
      /* disable ODE and out of reset*/
      /* diaable ODE and out of reset, ODE is connected to PC6.
         We should operate registers of parallel port C      */
         rstTSI(0xFF);
         
         /* block program  initialize connect memory */
         POINT = (unsigned long int *) (CS_TSI70840+CR);
         *POINT = 0x0002;   /* Init CR ,set Data Rate */
	 *POINT |= 0x0200;   /* BPM set */
	 *POINT |= 0x0010;   /* BPE,BPD=0x0 are seted simultaneously */
           

	
	  
         /* polling the BPE bit in the CR to indicate block program is completed */
	  wait = 1;
	  while (wait)
	  {
	  	wait = ((volatile unsigned long int)*POINT) & 0x0010;
	  } 	  
          
          rstTSI(0x2); /* pull the ODE UP */
          
	  
	  
	
     
}

void tsiChannelConnect
(
	unsigned short srcStream,  /* 5bits */
	unsigned short srcSlot,    /* 7bits */
	unsigned short dstStream,
	unsigned short dstSlot
)
{       
	unsigned long int *POINT;
	
	
	
	if (((srcStream < TSISTREAM)&& (srcSlot < TSISLOT))
	      && ((dstStream >= TSISTREAM) && (dstSlot >= TSISLOT)))
        {
        	/* select the connect memory */
        	POINT = (unsigned long int *)(CS_TSI70840+CONNECT_MEM+(dstStream<<7)+dstSlot);
        	/* set the connect memory */
        	*POINT = (CONMEM_OE | ((srcStream<<7)&0x0f80) | (srcSlot&0x007f));
        }
	else 
	{
		logMsg ("TSI slot or stream not exit\n",0,0,0,0,0,0);
	} 	 
}

void tsiChannelDisconnect
(
	unsigned short dstStream,
	unsigned short dstSlot
)
{
	 unsigned long int *POINT;
	
	 POINT = (unsigned long int *)(CS_TSI70840+CONNECT_MEM+(dstStream<<7)+dstSlot);
	 
	 if (((dstStream < TSISTREAM)&& (dstSlot < TSISLOT)))
	 {
	 	 *POINT &= ~(CONMEM_OE | (0x0f80) | (0x007f));	 	 								
	 }
	 else
	 {
	 	logMsg("TSI slot or stream not exist\n",0,0,0,0,0,0);
	 }	 	 
}

void tsiCrossCreate
(
	unsigned short firstStream,
	unsigned short firstSlot,
	unsigned short secondStream,
	unsigned short secondSlot
)
{
	tsiChannelDisconnect(firstStream,firstSlot);
	tsiChannelDisconnect(secondStream,secondSlot);
	
	tsiChannelConnect(firstStream,firstSlot,secondStream,secondSlot);
	tsiChannelConnect(secondStream,secondSlot,firstStream,firstSlot);	
}

void tsiCrossDestroy
(
	unsigned short firstStream,
	unsigned short firstSlot,
	unsigned short secondStream,
	unsigned short secondSlot
)
{
	tsiChannelDisconnect(firstStream,firstSlot);
	tsiChannelDisconnect(secondStream,secondSlot);
}

void tsiInputDelay 
(
        unsigned short DelayStream,
        unsigned short DelayNum   
        /* one refer to 0.5 clock period ,so two means 1.0 clock period */
)
{
        unsigned short temp;
	unsigned long int  *POINT;
	if (DelayStream<TSISTREAM)
	{
	    {
	    /* select corresponging ORn to the DelayStream */
            temp = DelayNum/4;
            POINT = (unsigned long int *)(CS_TSI70840+OR0+OROFFSEt*temp);
            temp = (Delay%4)*4;	
	    *POINT |= (unsigned int)(DelayNum<<temp);
            }
            {
            temp = ~(DelayNum&0x01);
            POINT = (unsigned long int *)(CS_TSI70840+FAR);
            *PINT |= (unsigned int)((Delay>>1)+(temp<<11))
            } 
        
        }
	else 
	{
		logMsg("stream not exist\n",0,0,0,0,0,0);
	}
	
}
/*
void dumpCross()
{
	 IDT72V90823REG * pTsiReg;
	 int i,j,first;
	 volatile unsigned short conMemTemp;
	 unsigned short srcStream;
	 unsigned short srcSlot;
	 
	 
	 first = 1;
	 
	 pTsiReg = idt90823TsiCtl.tsiReg;
	 
	 pTsiReg->cr = 0;
	 
	 for(i = 0 ;i < TSISTREAM ; i++)
	 {
	   pTsiReg->cr = i<<8;
	   
	   for (j = 0 ; j < TSISLOT ; j++)
	    {
	    	conMemTemp = pTsiReg->tsiMem[j];
	    	
	    	
	    	if (conMemTemp & 0x0008)
	    	{
	    		if(first == 1)
	    		{
	    			printf("\nIN(STREAM   , SLOT   )-->OUT(STREAM   ,SLOT   )\n");
	    			first = 0;
	    		}
	    		
    		
	    		srcStream = ((conMemTemp & 0x8000)>>15) | ((conMemTemp & 0x0007)<<1);
	    		srcSlot	  =  (conMemTemp & 0x7F00)>>8;
	    		
	    		printf("IN(       %d,      %d)-->OUT(       %d,     %d)\n",srcStream,srcSlot,i,j);
	    	}
	    }
	 }
	 printf("\n TimeSlot Dump OK\n");
}

*/