s3c9428 编写例程.src

三星单片机源码例程,做家电比较适合 S3C9428 编写例程.rar

	jp	eq,Set_high
	
	cp	TransIntv1,#0
	jp	ne,Chk_high1
	
	cp	TransIntv2,#0
	jp	ne,Chk_low1
	ld	r10,#0
	jp	Proc_trans
Chk_low1:
	cp	TransIntv2,#50h
	jp	ne,Chk_low2
	ld	r10,#1
	jp	Proc_trans
Chk_low2:
	cp	TransIntv2,#0a0h
	jp	ne,Chk_low3
	ld	r10,#2
	jp	Proc_trans	
Chk_low3:
	cp	TransIntv2,#0f0h
	jp	ne,Inc_intv
	ld	r10,#3
	jp	Proc_trans	
	
Set_high:
	clr	TransIntv2
	inc	TransIntv1	
Chk_high1:
	cp	TransIntv2,#40h
	jp	ne,Chk_high3
	ld	r10,#4
	jp	Proc_trans
Chk_high3:
	cp	TransIntv2,#90h
	jp	ne,Chk_high4
	ld	r10,#5
	jp	Proc_trans
Chk_high4:
	cp	TransIntv2,#0e0h	; interval counter - 1e0 ==> one cycle finish
	jp	ne,Inc_intv
	clr	TransIntv1
	clr	TransIntv2
	inc	TransCnt
	jp	Trans_End
	
Proc_trans:
	ld	r11,#TransBuf[r10]
	ld	siodata,r11	 
	or	siocon,#00001000b
	
Inc_intv:
	inc	TransIntv2

Trans_End:
	ret


;;;======================================================;;;

;;;======================================================;;;
;;;	         INTERRUPT SERVICE ROUTINE               ;;;
;;;======================================================;;;
 
INT_4208:				; 4208 has just one interrupt vector	
	ld	r0,t0conl
	and	r0,#00000011b
	cp	r0,#00000011b	
	jp	eq,INT_timer0		; t0con's pending bit & int. enable bit check
	
	ld	r0,siocon
	and	r0,#00000011b
	cp	r0,#00000011b	
	jp	eq,INT_sio		; siocon's pending bit & int. enable bit check
	
	
;;;============ SIO interrupt service routine ===========;;;

INT_sio:
	cp	TransOrReceive,#1
	jp	ne,Trans_Mode		; If trans mode, just pending clear
	
	ld	r0,siodata		; If receive mode, data processing
	ld	r1,SioCnt
	ld	#ReceiveData[r1],r0	; Storing received data
	inc	SioCnt
	cp	SioCnt,#6
	jp	ult,Receive_Mode

	clr	SioCnt
	
Receive_Mode:
	and	siocon,#11110010b	; pending, .2 , .3 bit clear
	or	siocon,#00001100b	; .2 , .3 bit set
	jp	Sio_End

Trans_Mode:
	and	siocon,#11111110b	; Pending bit clear	
	
Sio_End:
	iret	
	
	
;;;======== Timer 0 interrupt service routine ===========;;;

INT_timer0:
	and	t0conl,#11111110b	; pending clear

	call	Dsp_7_Seg
	
	cp	T0Count,#0
	jp	ne,Scan_call
	call	Time_Gen
	jr	T0Count_chk
	
Scan_call:
	cp	T0Count,#1
	jp	ne,None_call
	call	Key_Scan
	jr	T0Count_chk
	
None_call:
	call	reserved
	
T0Count_chk:
	inc	T0Count
	cp	T0Count,#6
	jr	ne,T0_end
	clr	T0Count		

T0_end:
	iret	
	
;;;------------------------------------------------------;;;
	
Time_Gen:
	inc	07h			; 10 msec interval
	cp	07h,#10
	jr	ult,Time_End
	clr	07h
msec:					; 100 msec interval
	inc	08h
	cp	08h,#10
	jr	ult,Time_End
	clr	08h
sec1:					; 1 sec interval
	inc	09h
	cp	09h,#10
	jr	ult,Time_End
	clr	09h
sec10:					; 10 sec interval
	inc	0Ah
	cp	0Ah,#10
	jr	ult,Time_End
	clr	0Ah
sec100:					; 100 sec interval
	inc	0Bh
	cp	0Bh,#10
	jr	ult,Time_End
	clr	0Bh
sec1000:				; 1000 sec interval
	inc	0Ch
	cp	0Ch,#10
	jr	ult,Time_End
	clr	0Ch
sec10000:				; 10000 sec interval
	inc	0Dh
	cp	0Dh,#10
	jr	ult,Time_End
	clr	0Dh
sec100000:				; 100000 sec interval
	inc	0Eh
	cp	0Eh,#10
	jr	ult,Time_End
	ld	0Fh,#0Eh	

Clear_Time:
	ld	@0Fh,#0
	dec	0Fh
	cp	0Fh,#07h
	jr	uge,Clear_Time
	
Time_End:
	ret
	
;;;------------------------------------------------------;;;

Key_Scan:
	cp	ScanDelay,#1
	jp	ult,Start_conv
	inc	ScanDelay
	cp	ScanDelay,#50		; 500ms delay
	jp	ult,Scan_End
	clr	ScanDelay

Start_conv:
	ld	adcon,#10110001b	; p0.7 --> ad conversion start
Conv_loop:
	tm	adcon,#00001000b	; Equal to upper 4 lines
	jp	z,Conv_loop
	
	clr	r1			; To store key value temporarily
	ld	r2,addatah
	
	rr	r2
	rr	r2
	and	r2,#00111111b		; For key scan, only high 6-bit is required
	
Extract_key:
	cp	r2,#1			; If no key input, end..
	jp	ule,Scan_End		; Monitoring only high 6-bit.

	cp	r2,#4			; If '0' key is pressed, conversion value is
	jp	ule,Prv_Chk		;  40h, but high 6-bit value is 4h.
	sub	r2,#4
	inc	r1
	jr	Extract_key
	
Prv_Chk:
	cp	r1,BeforeKey		; Check current key and previous key
	jp	ne,Not_same
	inc	KeyCnt
	cp	KeyCnt,#5		; Key pressing must be continued For 50ms
	jp	ult,Scan_End
	cp	KeyPTR,#19
	jp	eq,Buf_full
	inc	KeyPTR
	ld	r2,KeyPTR
	ld	#KeyBuf[r2],r1		; Store key value to buffer
	clr	KeyCnt			; After store, key count clear

	ld	ScanDelay,#1		; After store,, some delay should be required
					; To prevent key sensitivity
	jp	Scan_End
	
Buf_full:
	ld	KeyPTR,#0ffh		; If buffer is full, initialize buffer pointer
	jp	Scan_End
	
Not_same:
	ld	BeforeKey,r1		; Previous pressed-key is not same to current
	clr	KeyCnt			;  pressed-key
	
Scan_End:
	ret
	
;;;------------------------------------------------------;;;	
	
reserved:
	ret
	
;;;------------------------------------------------------;;;		
	
Dsp_7_Seg:
	cp	WhichDsp,#0		;;;;; '0' --> time display
	jp	ne,Is_menu
Is_time:
	ld	r0,#0eh			; eh --> 100000's sec
	sub	r0,T0Count
	ld	r2,@r0			; Extract time data
	add	r2,r2			; r2 <-- r2 * 2
	clr	r4
	ld	r5,r2
	jp	Data_conv
		
Is_menu:
	cp	WhichDsp,#1		;;;;; '1' --> menu display
	jp	ne,Is_receivedata
	clr	r0			; r0 --> multiply counter
	clr	r1			; r1 <-- (TestMode--) * 12
	ld	r2,TestMode
	
	cp	r2,#0eh	
	jp	ugt,Is_time	
	dec	r2
Mult_loop:
	add	r1,r2			; (TestMode--) * 12 --> MenuDat base
	inc	r0
	cp	r0,#12
	jr	ult,Mult_loop
	
	ld	r0,T0Count		; Which character of MenuDat will be displayed
	add	r0,r0			; r0 <-- r0 * 2
	
	clr	r4
	ld	r5,r1			; r1 --> MenuDat address base	
	add	r5,r0			; r0 --> which character offset
	ldc	r0,#MenuDat[rr4]
	ldc	r1,#MenuDat+1[rr4]
	jp	Display_Data
		
Is_receivedata:				;;;;; ReceiveData --> Adc/Capture/Check-sum
	ld	r0,T0Count
	ld	r1,#ReceiveData[r0]
	add	r1,r1			; r1 <-- r1 * 2
	clr	r4
	ld	r5,r1
	
Data_conv:
	ldc	r0,#ConDat[rr4]
	ldc	r1,#ConDat+1[rr4]
	
Display_Data:				;;; r0,r1 --> Displayed data store
	ld	r2,r0
	and	r2,#01000000b		; only p0.6 is required	
	and	p0,r0
	or	p0,r2
	ld	r2,r1
	and	r2,#00111111b		; p2.6/2.7 --> IIC
	and	p2,r1
	or	p2,r2			; Data display complete

	ld	r2,T0Count
	add	r2,r2
	clr	r4
	ld	r5,r2
	ldc	r0,#SegDat[rr4]
	ldc	r1,#SegDat+1[rr4]	; Extract which segment data
	ld	r2,r0			; r0 --> p0.5/0.4  r1 --> p1.0 ~ 1.3
	and	r2,#00110000b
	and	p0,r0
	or	p0,r2
	ld	p1,r1

	ret


;;;======================================================;;;
;;;----------------- End of the Program -----------------;;;
;;;======================================================;;;


	end