s3c9428 编写例程.src

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;;;================================================================;;;
;;;						                   ;;;
;;;	             KS86P4208 Micom Test Program                  ;;;
;;;						     		   ;;;
;;;			      	   	Programmed by SKID  	   ;;;
;;;								   ;;;
;;;	      Copyright (C) SAMSUNG ELECTRONICS CO. 1998           ;;;
;;;   	      ALL RIGHT RESERVED				   ;;;
;;;================================================================;;;

;;; Client-side program // Key scan,Time generation,Display service


	.include	"c:\smds2p\include\reg\86c4208.reg"
	
	org	0000h

	vector	00h,INT_4208	; 86C4208 has only one interrupt vector
	
	
;;;======================================================;;;

;;;======================================================;;;
;;;       Specific memory address renaming area          ;;;
;;;======================================================;;;

TimeBuf		.equ	07h	; To store time generated in Time_Gen() --> 07h ~ 0Fh
TransOrReceive	.equ	10h	; To separate trans mode and receive mode
T0Count		.equ	11h	; For multicall in timer0 interrupt
TimeCont	.equ	12h	; In Time_Gen(), to separate sec. min. ..
WhichDsp	.equ	13h	; Indicate that what kind of data be displayed

BeforeKey	.equ	14h	; For Key_Scan ruotine
KeyCnt		.equ	15h	; For Key_Scan ruotine

SioCnt		.equ	17h	; To count received data
KeyPTR		.equ	18h	; To point KEY Buffer

TestMode	.equ	19h	; Set by key-pressing (similar to DSP_BUF) --> 19h ~ 1Bh
TestMode1	.equ	1Ah	; sub test mode
TestMode2	.equ	1Bh	; Location of key 'F'
TransCnt	.equ	1Ch	; To count the number of trans
ReceiveData	.equ	1Dh	; To store received data from server-side --> 1Dh ~ 22h

KeyBuf		.equ	24h	; To store key data --> 24h ~ 37h
TransBuf	.equ	38h	; Trans data buffer --> 38h ~ 43h

BufOffset1	.equ	44h	; In Key_Srv routine
BufOffset2	.equ	45h	; In Key_Srv routine
TransIntv1	.equ	46h	; To control Transmit interval high 8-bit
TransIntv2	.equ	47h	; To control Transmit interval low 8-bit
ScanDelay	.equ	48h	; After storing key, some delay is required


;;;======================================================;;;

;;;======================================================;;;
;;;                   Define Word Area                   ;;;
;;;======================================================;;;

ConDat:		DW	0ffc0h,0fff9h,0bfe4h,0bff0h,0bfd9h,0bfd2h
		DW	0bfc2h,0ffd8h,0bfc0h,0bfd0h,0bfc8h,0bfc3h
		DW	0ffc6h,0bfe1h,0bfc6h,0bfceh 


;;;------------------------------------------------------;;;
SegDat:		DW	0dfffh,0efffh,0fff7h,0fffbh,0fffdh,0fffeh ; Which segment data


;;;------------------------------------------------------;;;
MenuDat:	DW	0bfd2h,0bfc7h,0bfe3h,0bfcch,0bfffh,0bfffh ; <-- 'STOP'
IDLE_DSP:	DW	0fff9h,0bfe1h,0ffc7h,0bfc6h,0bfffh,0bfffh
EXT_DSP:	DW	0bfc6h,0bfc7h,0bfffh,0fff9h,0bfebh,0bfc7h
BASIC_DSP:	DW	0bfc3h,0bfc8h,0bfd2h,0fff9h,0ffc6h,0bfc7h
CLK_DSP:	DW	0ffc6h,0ffc7h,0bfe3h,0ffc6h,0bfcbh,0bfffh
BUZ_DSP:	DW	0bfc3h,0ffc1h,0bfech,0bfech,0bfc6h,0bfefh
ZCD_DSP:	DW	0bfech,0ffc6h,0bfe1h,0bfffh,0bfffh,0bfffh
ADC_DSP:	DW	0bfc8h,0bfe1h,0ffc6h,0bfffh,0bfffh,0bfffh
T0_DSP:		DW	0bfc7h,0ffc0h,0bfffh,0bfffh,0bfffh,0bfffh
T1_DSP:		DW	0bfc7h,0fff9h,0bfffh,0bfffh,0bfffh,0bfffh
SIO_DSP:	DW	0bfd2h,0fff9h,0bfe3h,0bfffh,0bfffh,0bfffh
PWM_DSP:	DW	0bfcch,0ffc3h,0ffe1h,0ffcch,0ffd8h,0bfffh
IIC_DSP:	DW	0fff9h,0fff9h,0ffc6h,0bfffh,0bfffh,0bfffh
CHKSUM_DSP:	DW	0ffc6h,0bfc9h,0bfcbh,0bfd2h,0ffc1h,0bfffh


;;;======================================================;;;

;;;======================================================;;;
;;;        Initialize values of control registers        ;;;
;;;======================================================;;;

	org	0100h	
INITIAL:
	ld	sym,#00h		; Global/Fast interrupt disable -> sym
	ld	btcon,#10100010b	; Watch-dog disable
	ld	clkcon,#00011000b	; non-divided cpu clock
	ld	sp,#0c0h		; 4208 --> 00 ~ BF (After decrease, push data)

	ld	p0conh,#01101010b	; 0.7 - AD input(Key scan), rest - push-pull out
	ld	p0conl,#10010101b	; 0.2 ~ 0.0 - SIO setting
	ld	p1con,#10101010b	; p1 - push-pull out
	ld	p2conh,#11111010b	; 2.7,2.6 - IIC, 2.5,2.4 - push-pull out
	ld	p2conl,#10101010b	; 2.0 ~ 2.3 - push-pull out
	
	ld	t0data,#41h		; Interrupt interval == 1.667msec(10MHz base)
	ld	t0conl,#01000010	; Timer0 match interrupt
		
	ld	siocon,#00100110b	; Enable SIO, trans side (initial)
	ld	siops,#20		; setting baud rate

	ld	r0,#0	         	; RAM clear area setting
RAM_clr:
	clr	@r0
	inc	r0
	cp	r0,#0bfh
	jr	ule,RAM_clr
	
RAM_set:
	ld	KeyPTR,#0ffh
		
	ei


;;;======================================================;;;

;;;======================================================;;;
;;;						         ;;;
;;;                     MAIN  ROUTINE		         ;;;
;;;						         ;;;
;;;======================================================;;;

MAIN: 	
	nop

	call	Decision_WhichDsp	; What kind of data will be displayed?
	
	cp	TransOrReceive,#1	; Because of receive mode, the other routines
	jp	eq,MAIN			;  is not required.
	
	call	Key_Srv			; store key setting

	cp	TestMode1,#1		; Key setting complete?
	jp	ult,MAIN
	
	cp	TransCnt,#1		; Trans just one time
	jp	ult,Start_Trans
	
	ld	siocon,#10101110b	; Ready to receive data
	ld	p0conl,#10010100b	; SCK input mode
	ld	TransOrReceive,#1	; receive mode !
	jp	t,MAIN

Start_Trans:
	call	Trans_Data		; data trans to server-side

	jp	t,MAIN


;;;======================================================;;;

;;;======================================================;;;
;;;	             KEY SERVICE ROUTINE                 ;;;
;;;======================================================;;;

Key_Srv:
	ld	r3,KeyPTR
	cp	r3,#0ffh
	jp	eq,Key_Srv_End
	
	ld	r6,#KeyBuf[r3]	
	cp	TestMode,#0
	jp	ne,Chk_nextF
	
	cp	r6,#0fh
	jp	ne,Key_Srv_End
	ld	TestMode2,KeyPTR	; TestMode2 --> location of "F" in KEY BUFFER
	dec	r3
	cp	r3,#0ffh		; First data is 'F' ?
	jp	eq,Key_Srv_End
	
	ld	r6,#KeyBuf[r3]
	inc	r6
	ld	TestMode,r6		; main mode set
	jp	Key_Srv_End
	
Chk_nextF:
	cp	TestMode2,r3		; 'F' location? -- r3 --> KeyPTR
	jp	eq,Key_Srv_End
	
	cp	TestMode,#4
	jp	uge,Set_reg1
	
	ld	r11,#KeyBuf[r3]
	ld	TestMode1,r11
	inc	TestMode1		; sub mode set
	ld	r7,#TransBuf		; For indirect address
	ld	@r7,TestMode
	inc	r7
	ld	@r7,TestMode1		; STOP/IDLE/Ext.INT mode value set to TransBuf
	
	jp	Key_Srv_End
	
Set_reg1:				; 4 <= TestMode >= 8
	ld	r7,#TransBuf		; For indirect address
	add	r7,#2
	cp	TestMode,#8
	jp	ugt,Set_reg2
	ld	BufOffset1,#1
	ld	BufOffset2,#2
	jp	Set_TransBuf
Set_reg2:
	cp	TestMode,#0bh		; 9 <= TestMode >= B		
	jp	ugt,Set_reg3
	ld	BufOffset1,#3
	ld	BufOffset2,#4
	jp	Set_TransBuf
Set_reg3:
	cp	TestMode,#0ch		; TestMode == C		
	jp	ne,Set_reg4
	ld	BufOffset1,#5
	ld	BufOffset2,#6
	jp	Set_TransBuf
Set_reg4:
	cp	TestMode,#0dh		; TestMode == D		
	jp	ne,Set_reg5
	ld	BufOffset1,#7
	ld	BufOffset2,#8
	jp	Set_TransBuf
Set_reg5:				; Check-sum mode
	sub	r7,#2			; r7 <-- TransBuf base + 2
	ld	TestMode1,#1
	ld	@r7,TestMode
	inc	r7
	ld	@r7,TestMode1		
	jp	Key_Srv_End
	
Set_TransBuf:
	ld	r6,KeyPTR
	sub	r6,TestMode2		; r6 <-- KeyPTR - TestMode2
	cp	r6,BufOffset2		; Key input complete?
	jp	ne,Key_Srv_End
	
	sub	r3,BufOffset1		; r3 <-- KeyPTR - BufOffset1
Set_Transloop:
	ld	r6,#KeyBuf[r3]
	rl	r6			; shift to high 4-bit
	rl	r6
	rl	r6
	rl	r6
	or	r6,#00001111b
	inc	r3
	ld	r8,#KeyBuf[r3]
	or	r8,#11110000b
	and	r6,r8			; r6 <-- 1 byte register value
	ld	@r7,r6			; store to TransBuf
	inc	r3			; For extraction next data
	inc	r7
	ld	r9,TestMode2
	add	r9,BufOffset2
	cp	r3,r9
	jp	ult,Set_Transloop
	
	ld	r7,#TransBuf		; main test mode set & TestMode1 set
	ld	@r7,TestMode
	ld	TestMode1,#1
	inc	r7
	ld	@r7,TestMode1
	
Key_Srv_End:
	ret


;;;======================================================;;;

;;;======================================================;;;
;;;	           WhichDsp decision ROUTINE             ;;;
;;;======================================================;;;

Decision_WhichDsp:
	cp	TransOrReceive,#0	; In trans mode, menu and time are displayed
	jp	eq,Dsp_Trans
					; In receive mode, ADC/CAP/Check-Sum/time display
	cp	TestMode,#8		; display ADC data
	jp	eq,WhichDsp_adc
	
	cp	TestMode,#9		; display Capture data
	jp	eq,WhichDsp_cap
	
	cp	TestMode,#0dh		; display IIC data
	jp	eq,WhichDsp_iic
	
	cp	TestMode,#0eh		; display Check-Sum data
	jp	eq,WhichDsp_chksum		
	
	jp	Menu_Dsp
	
Dsp_Trans:
	cp	TestMode,#1
	jp	uge,Menu_Dsp
	ld	WhichDsp,#0		; time display --> trans mode & before ket set	
	jp	Decision_End	

Menu_Dsp:
	ld	WhichDsp,#1		; menu display --> trans mode & key setting
	jp	Decision_End		;                , receive mode & no dispaly data
	
WhichDsp_adc:
	ld	WhichDsp,#2
	jp	Decision_End
	
WhichDsp_cap:
	ld	WhichDsp,#3
	jp	Decision_End
	
WhichDsp_iic:
	ld	WhichDsp,#4
	jp	Decision_End
	
WhichDsp_chksum:
	ld	WhichDsp,#5

Decision_End:
	ret
	

;;;======================================================;;;

;;;======================================================;;;
;;;	           Data Transmit ROUTINE                 ;;;
;;;======================================================;;;

Trans_Data:
	cp	TransIntv2,#0ffh