csr_7button_demo_v2_1.lst

Button 一个国外大学生毕业设计,用的是AVR单片机

(0031) export Port_2_DriveMode_0_SHADE
(0032) export _Port_2_DriveMode_0_SHADE
(0033) export Port_2_DriveMode_1_SHADE
(0034) export _Port_2_DriveMode_1_SHADE
(0035) export Port_3_Data_SHADE
(0036) export _Port_3_Data_SHADE
(0037) 
(0038) 
(0039) export NO_SHADOW
(0040) export _NO_SHADOW
(0041) 
(0042) FLAG_CFG_MASK:      equ 10h         ;M8C flag register REG address bit mask
(0043) END_CONFIG_TABLE:   equ ffh         ;end of config table indicator
(0044) 
(0045) AREA psoc_config(rom, rel)
(0046) 
(0047) ;---------------------------------------------------------------------------
(0048) ; LoadConfigInit - Establish the start-up configuration (except for a few
(0049) ;                  parameters handled by boot code, like CPU speed). This
(0050) ;                  function can be called from user code, but typically it
(0051) ;                  is only called from boot.
(0052) ;
(0053) ;       INPUTS: None.
(0054) ;      RETURNS: Nothing.
(0055) ; SIDE EFFECTS: Registers are volatile: the A and X registers can be modified!
(0056) ;               In the large memory model currently only the page
(0057) ;               pointer registers listed below are modified.  This does
(0058) ;               not guarantee that in future implementations of this
(0059) ;               function other page pointer registers will not be
(0060) ;               modified.
(0061) ;          
(0062) ;               Page Pointer Registers Modified: 
(0063) ;               CUR_PP
(0064) ;
(0065) _LoadConfigInit:
(0066)  LoadConfigInit:
(0067)     RAM_PROLOGUE RAM_USE_CLASS_4
(0068)     
(0069) 	mov		[Port_1_Data_SHADE], 0h
    0293: 00       SWI   
(0070) 	mov		[Port_2_Data_SHADE], 0h
    0294: 55 01 00 MOV   [1],0
(0071) 	mov		[Port_2_DriveMode_0_SHADE], ffh
    0297: 55 02 FF MOV   [2],255
(0072) 	mov		[Port_2_DriveMode_1_SHADE], 0h
    029A: 55 03 00 MOV   [3],0
(0073) 	mov		[Port_3_Data_SHADE], 0h
    029D: 55 04 00 MOV   [4],0
(0074) 
(0075) 	lcall	LoadConfigTBL_csr_7button_demo_v2_1_Ordered
    02A0: 7C 01 AC LCALL 0x01AC
(0076) 	lcall	LoadConfig_csr_7button_demo_v2_1
    02A3: 7C 02 A7 LCALL 0x02A7
(0077) 
(0078)     RAM_EPILOGUE RAM_USE_CLASS_4
(0079)     ret
    02A6: 7F       RET   
(0080) 
(0081) ;---------------------------------------------------------------------------
(0082) ; Load Configuration csr_7button_demo_v2_1
(0083) ;
(0084) ;    Load configuration registers for csr_7button_demo_v2_1.
(0085) ;    IO Bank 0 registers a loaded first,then those in IO Bank 1.
(0086) ;
(0087) ;       INPUTS: None.
(0088) ;      RETURNS: Nothing.
(0089) ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
(0090) ;               modified as may the Page Pointer registers!
(0091) ;               In the large memory model currently only the page
(0092) ;               pointer registers listed below are modified.  This does
(0093) ;               not guarantee that in future implementations of this
(0094) ;               function other page pointer registers will not be
(0095) ;               modified.
(0096) ;          
(0097) ;               Page Pointer Registers Modified: 
(0098) ;               CUR_PP
(0099) ;
(0100) _LoadConfig_csr_7button_demo_v2_1:
(0101)  LoadConfig_csr_7button_demo_v2_1:
(0102)     RAM_PROLOGUE RAM_USE_CLASS_4
(0103) 
(0104) 	push	x
    02A7: 10       PUSH  X
(0105)     M8C_SetBank0                    ; Force bank 0
    02A8: 70 EF    AND   F,239
(0106)     mov     a, 0                    ; Specify bank 0
    02AA: 50 00    MOV   A,0
(0107)     asr     a                       ; Store in carry flag
    02AC: 67       ASR   A
(0108)                                     ; Load bank 0 table:
(0109)     mov     A, >LoadConfigTBL_csr_7button_demo_v2_1_Bank0
    02AD: 50 02    MOV   A,2
(0110)     mov     X, <LoadConfigTBL_csr_7button_demo_v2_1_Bank0
    02AF: 57 21    MOV   X,33
(0111)     lcall   LoadConfig              ; Load the bank 0 values
    02B1: 7C 02 C0 LCALL 0x02C0
(0112) 
(0113)     mov     a, 1                    ; Specify bank 1
    02B4: 50 01    MOV   A,1
(0114)     asr     a                       ; Store in carry flag
    02B6: 67       ASR   A
(0115)                                     ; Load bank 1 table:
(0116)     mov     A, >LoadConfigTBL_csr_7button_demo_v2_1_Bank1
    02B7: 50 02    MOV   A,2
(0117)     mov     X, <LoadConfigTBL_csr_7button_demo_v2_1_Bank1
    02B9: 57 56    MOV   X,86
(0118)     lcall   LoadConfig              ; Load the bank 1 values
    02BB: 7C 02 C0 LCALL 0x02C0
(0119) 
(0120) 	pop		x
    02BE: 20       POP   X
(0121) 
(0122)     RAM_EPILOGUE RAM_USE_CLASS_4
(0123)     ret
    02BF: 7F       RET   
(0124) 
(0125) 
(0126) 
(0127) 
(0128) ;---------------------------------------------------------------------------
(0129) ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
(0130) ;              pairs. Terminate on address=0xFF.
(0131) ;
(0132) ;  INPUTS:  [A,X] points to the table to be loaded
(0133) ;           Flag Register Carry bit encodes the Register Bank
(0134) ;           (Carry=0 => Bank 0; Carry=1 => Bank 1)
(0135) ;
(0136) ;  RETURNS: nothing.
(0137) ;
(0138) ;  STACK FRAME:  X-4 I/O Bank 0/1 indicator
(0139) ;                X-3 Temporary store for register address
(0140) ;                X-2 LSB of config table address
(0141) ;                X-1 MSB of config table address
(0142) ;
(0143) LoadConfig:
(0144)     RAM_PROLOGUE RAM_USE_CLASS_2
(0145)     add     SP, 2                   ; Set up local vars
    02C0: 38 02    ADD   SP,2
(0146)     push    X                       ; Save config table address on stack
    02C2: 10       PUSH  X
(0147)     push    A
    02C3: 08       PUSH  A
(0148)     mov     X, SP
    02C4: 4F       MOV   X,SP
(0149)     mov     [X-4], 0                ; Set default Destination to Bank 0
    02C5: 56 FC 00 MOV   [X-4],0
(0150)     jnc     .BankSelectSaved        ; Carry says Bank 0 is OK
    02C8: D0 04    JNC   0x02CD
(0151)     mov     [X-4], 1                ; No Carry: default to Bank 1
    02CA: 56 FC 01 MOV   [X-4],1
(0152) .BankSelectSaved:
(0153)     pop     A
    02CD: 18       POP   A
(0154)     pop     X
    02CE: 20       POP   X
(0155) 
(0156) LoadConfigLp:
(0157)     M8C_SetBank0                    ; Switch to bank 0
    02CF: 70 EF    AND   F,239
(0158)     M8C_ClearWDT                    ; Clear the watchdog for long inits
    02D1: 62 E3 00 MOV   REG[227],0
(0159)     push    X                       ; Preserve the config table address
    02D4: 10       PUSH  X
(0160)     push    A
    02D5: 08       PUSH  A
(0161)     romx                            ; Load register address from table
    02D6: 28       ROMX  
(0162)     cmp     A, END_CONFIG_TABLE     ; End of table?
    02D7: 39 FF    CMP   A,255
(0163)     jz      EndLoadConfig           ;   Yes, go wrap it up
    02D9: A0 1F    JZ    0x02F9
(0164)     mov     X, SP                   ;
    02DB: 4F       MOV   X,SP
(0165)     tst     [X-4], 1                ; Loading IO Bank 1?
    02DC: 48 FC 01 TST   [X-4],1
(0166)     jz      .IOBankNowSet           ;    No, Bank 0 is fine
    02DF: A0 03    JZ    0x02E3
(0167)     M8C_SetBank1                    ;   Yes, switch to Bank 1
    02E1: 71 10    OR    F,16
(0168) .IOBankNowSet:
(0169)     mov     [X-3], A                ; Stash the register address
    02E3: 54 FD    MOV   [X-3],A
(0170)     pop     A                       ; Retrieve the table address
    02E5: 18       POP   A
(0171)     pop     X
    02E6: 20       POP   X
(0172)     inc     X                       ; Advance to the data byte
    02E7: 75       INC   X
(0173)     adc     A, 0
    02E8: 09 00    ADC   A,0
(0174)     push    X                       ; Save the config table address again
    02EA: 10       PUSH  X
(0175)     push    A
    02EB: 08       PUSH  A
(0176)     romx                            ; load config data from the table
    02EC: 28       ROMX  
(0177)     mov     X, SP                   ; retrieve the register address
    02ED: 4F       MOV   X,SP
(0178)     mov     X, [X-3]
    02EE: 59 FD    MOV   X,[X-3]
(0179)     mov     reg[X], A               ; Configure the register
    02F0: 61 00    MOV   REG[X+0],A
(0180)     pop     A                       ; retrieve the table address
    02F2: 18       POP   A
(0181)     pop     X
    02F3: 20       POP   X
(0182)     inc     X                       ; advance to next table entry
    02F4: 75       INC   X
(0183)     adc     A, 0
    02F5: 09 00    ADC   A,0
(0184)     jmp     LoadConfigLp            ; loop to configure another register
    02F7: 8F D7    JMP   0x02CF
(0185) EndLoadConfig:
(0186)     add     SP, -4
    02F9: 38 FC    ADD   SP,252
    02FB: 70 3F    AND   F,63
(0187)     RAM_EPILOGUE RAM_USE_CLASS_2
    02FD: 71 C0    OR    F,192
(0188)     ret
    02FF: 7F       RET   
FILE: lib\lcd_1.asm
(0001) ;;*****************************************************************************
(0002) ;;*****************************************************************************
(0003) ;;  FILENAME:   LCD_1.asm
(0004) ;;  Version: 1.4, Updated on 2005/09/30 at 10:52:22
(0005) ;;  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
(0006) ;;
(0007) ;;  DESCRIPTION: LCD User Module software implementation file
(0008) ;;               for 22/24/25/26/27xxx PSoC family of devices.
(0009) ;;
(0010) ;; This set of functions is written for the common 2 and 4 line
(0011) ;; LCDs that use the Hitachi HD44780A controller.
(0012) ;;
(0013) ;;  LCD connections to PSoC port
(0014) ;;
(0015) ;;    PX.0 ==> LCD D4
(0016) ;;    PX.1 ==> LCD D5
(0017) ;;    PX.2 ==> LCD D6
(0018) ;;    PX.3 ==> LCD D7
(0019) ;;    PX.4 ==> LCD E
(0020) ;;    PX.5 ==> LCD RS
(0021) ;;    PX.6 ==> LCD R/W
(0022) ;;
(0023) ;;  NOTE: User Module APIs conform to the fastcall16 convention for marshalling
(0024) ;;        arguments and observe the associated "Registers are volatile" policy.
(0025) ;;        This means it is the caller's responsibility to preserve any values
(0026) ;;        in the X and A registers that are still needed after the API functions
(0027) ;;        returns. For Large Memory Model devices it is also the caller's 
(0028) ;;        responsibility to perserve any value in the CUR_PP, IDX_PP, MVR_PP and 
(0029) ;;        MVW_PP registers. Even though some of these registers may not be modified
(0030) ;;        now, there is no guarantee that will remain the case in future releases.
(0031) ;;-----------------------------------------------------------------------------
(0032) ;;  Copyright (c) Cypress MicroSystems 2001-2003. All Rights Reserved.
(0033) ;;*****************************************************************************
(0034) ;;*****************************************************************************
(0035) 
(0036) include "m8c.inc"
(0037) include "memory.inc"
(0038) include "LCD_1.inc"
(0039) 
(0040) ;-----------------------------------------------
(0041) ;  Global Symbols
(0042) ;-----------------------------------------------
(0043) 
(0044) export   LCD_1_Start
(0045) export  _LCD_1_Start
(0046) export   LCD_1_Init
(0047) export  _LCD_1_Init
(0048) 
(0049) export   LCD_1_WriteData
(0050) export  _LCD_1_WriteData
(0051) 
(0052) export   LCD_1_Control
(0053) export  _LCD_1_Control
(0054) 
(0055) export  LCD_1_PrString
(0056) export _LCD_1_PrString
(0057) 
(0058) export  LCD_1_PrCString
(0059) export _LCD_1_PrCString
(0060) 
(0061) export  LCD_1_Position
(0062) export _LCD_1_Position
(0063) 
(0064) export  LCD_1_PrHexByte
(0065) export _LCD_1_PrHexByte
(0066) 
(0067) export  LCD_1_PrHexInt
(0068) export _LCD_1_PrHexInt
(0069) 
(0070) export  LCD_1_Delay50uTimes
(0071) export _LCD_1_Delay50uTimes
(0072) 
(0073) export  LCD_1_Delay50u
(0074) export _LCD_1_Delay50u
(0075) 
(0076) ;-----------------------------------------------
(0077) ; If bargraph functions not required, don't
(0078) ; export the function names.
(0079) ;-----------------------------------------------
(0080) 
(0081) IF (LCD_1_BARGRAPH_ENABLE)
(0082) export  LCD_1_InitBG
(0083) export _LCD_1_InitBG
(0084) 
(0085) export  LCD_1_InitVBG
(0086) export _LCD_1_InitVBG
(0087) 
(0088) ; NOTE: The two functions,
(0089) ;
(0090) ;    LCD_1_DrawVBG and
(0091) ;    LCD_1_DrawBG
(0092) ;
(0093) ; are implemented using both fastcall16 and legacy fastcall16 because they
(0094) ; fall into a special and rare case where the calling sequences specified
(0095) ; by the two disciplines are incompatible. The fastcall16 versions are
(0096) ; provided for both C and Assembly users in all memory models. The legacy
(0097) ; fastcall16 versions are provided only to support existing small memory
(0098) ; model assembly language code---they do not work in the large memory
(0099) ; model.
(0100) ;
(0101) ; ** The legacy fastcall16 versions are provided on a temporary basis to
(0102) ; ** ease the transition to the 4.2 release of PSoC Designer. Their use is
(0103) ; ** deprecated and thier status is "No Further Maintenance".
(0104) ;
(0105) ; The fastcall16 versions of these functions are distinguished by a
(0106) ; leading underscore in the name. The legacy fastcall16 names (which appear
(0107) ; in this comment) do not have the leading underscore. Details on the
(0108) ; calling sequence to be used for fastcall16 are given in the user module
(0109) ; datasheet.