📄 csr_1.lis
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; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
;------------------------
; Constant Definitions
;------------------------
AREA UserModules (ROM, REL, CON)
0001 LSB: equ 1
0000 MSB: equ 0
0000
0000 ;---------------------------------
0000 ; Tables below generated by Wizard
0000 ;---------------------------------
0000
0000 ; The Switch Table consist of two bytes for each switch. The first byte is the
0000 ; port number and the second is the bit mask for the bit. (Not the bit number)
0000 ; For example an entry for port 2 bit 3 (P2[3]) would be "dw 0x0208"
0000 ;
0000 ; This table consist of 0x7 switches.
0000 CSR_1_Switch_Table:
0000 _CSR_1_Switch_Table:
0000 0110 dw 0x0110 // Port 1 Bit 4
0002 0140 dw 0x0140 // Port 1 Bit 6
0004 0301 dw 0x0301 // Port 3 Bit 0
0006 0304 dw 0x0304 // Port 3 Bit 2
0008 0308 dw 0x0308 // Port 3 Bit 3
000A 0302 dw 0x0302 // Port 3 Bit 1
000C 0108 dw 0x0108 // Port 1 Bit 3
000E
000E
000E .SECTION
000E ;-----------------------------------------------------------------------------
000E ; FUNCTION NAME: CSR_1_Start(void)
000E ;
000E ; DESCRIPTION:
000E ; Initializes registers and turns on the comparitor.
000E ;
000E ;-----------------------------------------------------------------------------
000E ;
000E ; ARGUMENTS:
000E ; None
000E ;
000E ; RETURNS: None.
000E ; SIDE EFFECTS:
000E ; The A and X registers may be modified by this or future implementations
000E ; of this function. The same is true for all RAM page pointer registers in
000E ; the Large Memory Model. When necessary, it is the calling function's
000E ; responsibility to perserve their values across calls to fastcall16
000E ; functions.
000E ;
000E CSR_1_Start:
000E _CSR_1_Start:
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
IF ( SYSTEM_LARGE_MEMORY_MODEL )
000E 62D013 mov reg[CUR_PP], >CSR_1_bPWMPeriod
ENDIF
IF (CSR_1_Method)
// Period Method
0011 551310 mov [CSR_1_bPWMPeriod], 0x10
0014 622110 mov reg[CSR_1_PWM_PERIOD_REG],0x10 ; Set period (default to 10 cycles)
0017 62220E mov reg[CSR_1_PWM_COMPARE_REG],0x0E ; Set compare
001A 62FD80 mov reg[DAC_D], 0x80 ; Set Dac at medium level
ELSE
// Frequency Method
mov [CSR_1_bPWMPeriod], 0xFF
mov reg[CSR_1_PWM_PERIOD_REG],0xFF ; Set period
mov reg[CSR_1_PWM_COMPARE_REG],0xFD ; Set compare
mov reg[DAC_D], 0x80 ; Set Dac at medium level
ENDIF
001D 626600 mov reg[CMP_CR1],0x00 ; CLDIS0 - synced comparator input enters mux
0020
0020 62E600 mov reg[DEC_CR0],0x00 ; IGEN0 - output of comparator is not ANDed with a PWM
0023
0023 43B003 or reg[RDI0RI],0x03 ; Connect Row 0 to GIO0[4]
0026
0026
0026 7110 or F, FLAG_XIO_MASK
0028 62FD03 mov reg[DAC_CR],0x03 ; Range high = 0x08, Reset on G00[4] = 0x02, Dac Enable = 0x01
002B 626408 mov reg[CMP_GO_EN],0x08 ; GOO[4] out = 0x08, SEL0 - now sends output of IGEN0
002E 43D210 or reg[GDI_O_OU],0x10 ; THIS SHOULD WORK IN THE XML DEBUG
0031
0031 62D800 mov reg[MUX_CR0],0x00 ; Make sure all switches are off by default
0034 62D900 mov reg[MUX_CR1],0x00
0037 62DA00 mov reg[MUX_CR2],0x00
003A 62DB00 mov reg[MUX_CR3],0x00
003D
003D 436B04 or reg[CLK_CR3],0x04 ; Use Sysclock direct for Column 0
0040
0040 62223C mov reg[CSR_1_PWM_OUT_REG],0x3C ; Output PWM compare to row 0, TC to row 3
0043
IF (CSR_1_Method)
// Period Method
0043 62211C mov reg[CSR_1_PWM_IN_REG],0x1C ; Data = 0x10 (High) and Clock = 0x0C (Row_Input_0)
0046 6225FC mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0xF0 (Row_input_3) and Clock = 0x0X (SysClk direct see output reg)
0049 62293C mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (SysClk direct see output reg)
004C 6226C0 mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0xC0 ; Use SysClk direct
004F 622AC0 mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0xC0 ; Use SysClk direct
0052
ELSE
// Frequency Method
mov reg[OSC_CR4],0x00 ; Use Sysclock as input to VC3
mov reg[OSC_CR3],0xFF ; Set VC3 to 255
mov reg[CSR_1_PWM_IN_REG],0x11 ; Data = 0x10 (High) and Clock = 0x01 (VC3)
mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0x80 (Row_input_3) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0x00 ; Sync to SysClk and no outputs
mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0x00 ; Sync to SysClk and no outputs
ENDIF
0052 41B27F and reg[RDI0IS], ~0x80 ; Make sure input 'A' to LUT3 is RO[3]
0055 41B40F and reg[RDI0LT1],~0xF0
0058 43B440 or reg[RDI0LT1],0x40 ; Combine PWM compare and ~PWM TC running to GPIO: ~A&B (LUT3)
005B 41B60F and reg[RDI0RO1],~0xF0
005E 43B680 or reg[RDI0RO1],0x80 ; Output LUT3 to global out odd 7
0061 43D280 or reg[GDI_O_OU],0x80 ; Drive global out odd 7 onto global in odd 7
0064 43B0C0 or reg[RDI0RI],0xC0 ; Row input 3 comes from global in odd 7
0067 41B1F7 and reg[RDI0SYN],~0x08 ; Row input 3 passes with synchronization
006A
006A 70EF and F, ~FLAG_XIO_MASK
006C
006C 9001 call CSR_1_ClearSwitches ; Loop through all keys and deactivate
006E ; This also puts pin in proper mode.
006E
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
006E 7F ret
006F .ENDSECTION
006F
006F
006F
006F
006F .SECTION
006F ;-----------------------------------------------------------------------------
006F ; FUNCTION NAME: CSR_1_ClearSwitches(void)
006F ;
006F ; DESCRIPTION:
006F ; Clears all switches to the non-sampling state.
006F ;
006F ;-----------------------------------------------------------------------------
006F ;
006F ; ARGUMENTS: None.
006F ; RETUR⌨️ 快捷键说明
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