📄 psocconfigtbl.lis
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0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_NOWRITE: equ 08h ; MASK: Vcc below Flash Write level
0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
0000
00E5 ADC0_TR: equ E5h ; ADC Column 0 Trim Register
00E6 ADC1_TR: equ E6h ; ADC Column 1 Trim Register
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
00FA FLS_PR1: equ FAh ; Flash Program Register 1 (RW)
0003 FLS_PR1_BANK: equ 03h ; MASK: Select Active Flash Bank
0000
00FD DAC_CR: equ FDh ; Analog Mux DAC Control Register
0008 DAC_CR_IRANGE: equ 08h ; MASK: Sets the DAC Range low or high
0006 DAC_CR_OSCMODE: equ 06h ; MASK: Defines the reset mode for AMux
0001 DAC_CR_ENABLE: equ 01h ; MASK: Enable/Disable DAC function
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export LoadConfigTBL_csr_7button_demo_v2_1_Bank1
export LoadConfigTBL_csr_7button_demo_v2_1_Bank0
export LoadConfigTBL_csr_7button_demo_v2_1_Ordered
AREA lit(rom, rel)
0000 LoadConfigTBL_csr_7button_demo_v2_1_Ordered:
0000 ; Ordered Global Register values
0000 7110 or F, FLAG_XIO_MASK
0002 6200FF mov reg[00h], ffh ; Port_0_DriveMode_0 register (PRT0DM0)
0005 620100 mov reg[01h], 00h ; Port_0_DriveMode_1 register (PRT0DM1)
0008 70EF and F, ~FLAG_XIO_MASK
000A 620300 mov reg[03h], 00h ; Port_0_DriveMode_2 register (PRT0DM2)
000D 620200 mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
0010 7110 or F, FLAG_XIO_MASK
0012 620200 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
0015 620300 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
0018 70EF and F, ~FLAG_XIO_MASK
001A 620100 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
001D 7110 or F, FLAG_XIO_MASK
001F 6204A7 mov reg[04h], a7h ; Port_1_DriveMode_0 register (PRT1DM0)
0022 620558 mov reg[05h], 58h ; Port_1_DriveMode_1 register (PRT1DM1)
0025 70EF and F, ~FLAG_XIO_MASK
0027 620758 mov reg[07h], 58h ; Port_1_DriveMode_2 register (PRT1DM2)
002A 620600 mov reg[06h], 00h ; Port_1_GlobalSelect register (PRT1GS)
002D 7110 or F, FLAG_XIO_MASK
002F 620600 mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
0032 620700 mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
0035 70EF and F, ~FLAG_XIO_MASK
0037 620500 mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
003A 7110 or F, FLAG_XIO_MASK
003C 6208FF mov reg[08h], ffh ; Port_2_DriveMode_0 register (PRT2DM0)
003F 620900 mov reg[09h], 00h ; Port_2_DriveMode_1 register (PRT2DM1)
0042 70EF and F, ~FLAG_XIO_MASK
0044 620B00 mov reg[0bh], 00h ; Port_2_DriveMode_2 register (PRT2DM2)
0047 620A00 mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
004A 7110 or F, FLAG_XIO_MASK
004C 620A00 mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
004F 620B00 mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
0052 70EF and F, ~FLAG_XIO_MASK
0054 620900 mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
0057 7110 or F, FLAG_XIO_MASK
0059 620C00 mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
005C 620D0F mov reg[0dh], 0fh ; Port_3_DriveMode_1 register (PRT3DM1)
005F 70EF and F, ~FLAG_XIO_MASK
0061 620F0F mov reg[0fh], 0fh ; Port_3_DriveMode_2 register (PRT3DM2)
0064 620E00 mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
0067 7110 or F, FLAG_XIO_MASK
0069 620E00 mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
006C 620F00 mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
006F 70EF and F, ~FLAG_XIO_MASK
0071 620D00 mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
0074 7F ret
0075 LoadConfigTBL_csr_7button_demo_v2_1_Bank0:
0075 ; Global Register values
0075 6009 db 60h, 09h ; AnalogColumnInputSelect register (AMX_IN)
0077 6400 db 64h, 00h ; AnalogComparatorControl0 register (CMP_CR0)
0079 6600 db 66h, 00h ; AnalogComparatorControl1 register (CMP_CR1)
007B 6100 db 61h, 00h ; AnalogMuxBusConfig register (AMUXCFG)
007D E610 db e6h, 10h ; DecimatorControl_0 register (DEC_CR0)
007F E700 db e7h, 00h ; DecimatorControl_1 register (DEC_CR1)
0081 D600 db d6h, 00h ; I2CConfig register (I2CCFG)
0083 6200 db 62h, 00h ; PWM_Control register (PWM_CR)
0085 B003 db b0h, 03h ; Row_0_InputMux register (RDI0RI)
0087 B100 db b1h, 00h ; Row_0_InputSync register (RDI0SYN)
0089 B200 db b2h, 00h ; Row_0_LogicInputAMux register (RDI0IS)
008B B333 db b3h, 33h ; Row_0_LogicSelect_0 register (RDI0LT0)
008D B433 db b4h, 33h ; Row_0_LogicSelect_1 register (RDI0LT1)
008F B500 db b5h, 00h ; Row_0_OutputDrive_0 register (RDI0SRO0)
0091 B600 db b6h, 00h ; Row_0_OutputDrive_1 register (RDI0SRO1)
0093 ; Instance name CSR_1, User Module CSR
0093 ; Instance name CSR_1, Block Name CMP(ACE00)
0093 724F db 72h, 4fh ;CSR_1_ACE_CONTROL1_REG(ACE00CR1)
0095 7300 db 73h, 00h ;CSR_1_ACE_CONTROL2_REG(ACE00CR2)
0097 ; Instance name CSR_1, Block Name Counter16_LSB(DBB01)
0097 2702 db 27h, 02h ;CSR_1_CTR_CONTROL_LSB_REG(DBB01CR0)
0099 2500 db 25h, 00h ;CSR_1_CTR_PERIOD_LSB_REG(DBB01DR1)
009B 2600 db 26h, 00h ;CSR_1_CTR_COMPARE_LSB_REG(DBB01DR2)
009D ; Instance name CSR_1, Block Name Counter16_MSB(DCB02)
009D 2B00 db 2bh, 00h ;CSR_1_CTR_CONTROL_MSB_REG(DCB02CR0)
009F 2900 db 29h, 00h ;CSR_1_CTR_PERIOD_MSB_REG(DCB02DR1)
00A1 2A00 db 2ah, 00h ;CSR_1_CTR_COMPARE_MSB_REG(DCB02DR2)
00A3 ; Instance name CSR_1, Block Name PWM(DBB00)
00A3 2300 db 23h, 00h ;CSR_1_PWM_CONTROL_REG(DBB00CR0)
00A5 2100 db 21h, 00h ;CSR_1_PWM_PERIOD_REG(DBB00DR1)
00A7 2200 db 22h, 00h ;CSR_1_PWM_COMPARE_REG(DBB00DR2)
00A9 ; Instance name LCD_1, User Module LCD
00A9 FF db ffh
00AA LoadConfigTBL_csr_7button_demo_v2_1_Bank1:
00AA ; Global Register values
00AA 6100 db 61h, 00h ; AnalogClockSelect1 register (CLK_CR1)
00AC 6000 db 60h, 00h ; AnalogColumnClockSelect register (CLK_CR0)
00AE 6200 db 62h, 00h ; AnalogIOControl_0 register (ABF_CR0)
00B0 6733 db 67h, 33h ; AnalogLUTControl0 register (ALT_CR0)
00B2 6400 db 64h, 00h ; ComparatorGlobalOutEn register (CMP_GO_EN)
00B4 FD00 db fdh, 00h ; DAC_Control register (DAC_CR)
00B6 D100 db d1h, 00h ; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
00B8 D300 db d3h, 00h ; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
00BA D000 db d0h, 00h ; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
00BC D210 db d2h, 10h ; GlobalDigitalInterconnect_Drive_Odd_Output register (GDI_O_OU)
00BE E100 db e1h, 00h ; OscillatorControl_1 register (OSC_CR1)
00C0 E200 db e2h, 00h ; OscillatorControl_2 register (OSC_CR2)
00C2 DF00 db dfh, 00h ; OscillatorControl_3 register (OSC_CR3)
00C4 DE00 db deh, 00h ; OscillatorControl_4 register (OSC_CR4)
00C6 DD00 db ddh, 00h ; OscillatorGlobalBusEnableControl register (OSC_GO_EN)
00C8 D800 db d8h, 00h ; Port_0_MUXBusCtrl register (MUX_CR0)
00CA D958 db d9h, 58h ; Port_1_MUXBusCtrl register (MUX_CR1)
00CC DA00 db dah, 00h ; Port_2_MUXBusCtrl register (MUX_CR2)
00CE DB0F db dbh, 0fh ; Port_3_MUXBusCtrl register (MUX_CR3)
00D0 ; Instance name CSR_1, User Module CSR
00D0 ; Instance name CSR_1, Block Name CMP(ACE00)
00D0 ; Instance name CSR_1, Block Name Counter16_LSB(DBB01)
00D0 2401 db 24h, 01h ;CSR_1_CTR_FUNC_LSB_REG(DBB01FN)
00D2 258C db 25h, 8ch ;CSR_1_CTR_INPUT_LSB_REG(DBB01IN)
00D4 2600 db 26h, 00h ;CSR_1_CTR_OUTPUT_LSB_REG(DBB01OU)
00D6 ; Instance name CSR_1, Block Name Counter16_MSB(DCB02)
00D6 2821 db 28h, 21h ;CSR_1_CTR_FUNC_MSB_REG(DCB02FN)
00D8 293C db 29h, 3ch ;CSR_1_CTR_INPUT_MSB_REG(DCB02IN)
00DA 2A00 db 2ah, 00h ;CSR_1_CTR_OUTPUT_MSB_REG(DCB02OU)
00DC ; Instance name CSR_1, Block Name PWM(DBB00)
00DC 2021 db 20h, 21h ;CSR_1_PWM_FUNC_REG(DBB00FN)
00DE 2111 db 21h, 11h ;CSR_1_PWM_IN_REG(DBB00IN)
00E0 2244 db 22h, 44h ;CSR_1_PWM_OUT_REG(DBB00OU)
00E2 ; Instance name LCD_1, User Module LCD
00E2 FF db ffh
00E3
00E3
00E3 ; PSoC Configuration file trailer PsocConfig.asm
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