📄 psocconfig.lis
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ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
0015 7F ret
0016
0016 ;---------------------------------------------------------------------------
0016 ; Load Configuration csr_7button_demo_v2_1
0016 ;
0016 ; Load configuration registers for csr_7button_demo_v2_1.
0016 ; IO Bank 0 registers a loaded first,then those in IO Bank 1.
0016 ;
0016 ; INPUTS: None.
0016 ; RETURNS: Nothing.
0016 ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
0016 ; modified as may the Page Pointer registers!
0016 ; In the large memory model currently only the page
0016 ; pointer registers listed below are modified. This does
0016 ; not guarantee that in future implementations of this
0016 ; function other page pointer registers will not be
0016 ; modified.
0016 ;
0016 ; Page Pointer Registers Modified:
0016 ; CUR_PP
0016 ;
0016 _LoadConfig_csr_7button_demo_v2_1:
0016 LoadConfig_csr_7button_demo_v2_1:
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
0016 10 push x
0017 70EF and F, ~FLAG_XIO_MASK
0019 5000 mov a, 0 ; Specify bank 0
001B 67 asr a ; Store in carry flag
001C ; Load bank 0 table:
001C 5000 mov A, >LoadConfigTBL_csr_7button_demo_v2_1_Bank0
001E 5700 mov X, <LoadConfigTBL_csr_7button_demo_v2_1_Bank0
0020 7C002F lcall LoadConfig ; Load the bank 0 values
0023
0023 5001 mov a, 1 ; Specify bank 1
0025 67 asr a ; Store in carry flag
0026 ; Load bank 1 table:
0026 5000 mov A, >LoadConfigTBL_csr_7button_demo_v2_1_Bank1
0028 5700 mov X, <LoadConfigTBL_csr_7button_demo_v2_1_Bank1
002A 7C002F lcall LoadConfig ; Load the bank 1 values
002D
002D 20 pop x
002E
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
002E 7F ret
002F
002F
002F
002F
002F ;---------------------------------------------------------------------------
002F ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
002F ; pairs. Terminate on address=0xFF.
002F ;
002F ; INPUTS: [A,X] points to the table to be loaded
002F ; Flag Register Carry bit encodes the Register Bank
002F ; (Carry=0 => Bank 0; Carry=1 => Bank 1)
002F ;
002F ; RETURNS: nothing.
002F ;
002F ; STACK FRAME: X-4 I/O Bank 0/1 indicator
002F ; X-3 Temporary store for register address
002F ; X-2 LSB of config table address
002F ; X-1 MSB of config table address
002F ;
002F LoadConfig:
IF ( RAM_USE_CLASS_2 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_2 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_2 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_2 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
002F 3802 add SP, 2 ; Set up local vars
0031 10 push X ; Save config table address on stack
0032 08 push A
0033 4F mov X, SP
0034 56FC00 mov [X-4], 0 ; Set default Destination to Bank 0
0037 D004 jnc .BankSelectSaved ; Carry says Bank 0 is OK
0039 56FC01 mov [X-4], 1 ; No Carry: default to Bank 1
003C .BankSelectSaved:
003C 18 pop A
003D 20 pop X
003E
003E LoadConfigLp:
003E 70EF and F, ~FLAG_XIO_MASK
0040 62E300 mov reg[RES_WDT], 00h
0043 10 push X ; Preserve the config table address
0044 08 push A
0045 28 romx ; Load register address from table
0046 39FF cmp A, END_CONFIG_TABLE ; End of table?
0048 A01F jz EndLoadConfig ; Yes, go wrap it up
004A 4F mov X, SP ;
004B 48FC01 tst [X-4], 1 ; Loading IO Bank 1?
004E A003 jz .IOBankNowSet ; No, Bank 0 is fine
0050 7110 or F, FLAG_XIO_MASK
0052 .IOBankNowSet:
0052 54FD mov [X-3], A ; Stash the register address
0054 18 pop A ; Retrieve the table address
0055 20 pop X
0056 75 inc X ; Advance to the data byte
0057 0900 adc A, 0
0059 10 push X ; Save the config table address again
005A 08 push A
005B 28 romx ; load config data from the table
005C 4F mov X, SP ; retrieve the register addr⌨️ 快捷键说明
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