📄 csr_1hl.lis
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0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_X_POINTS_TO_INDEXPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro RAM_EPILOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE PRV_PP
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 REG_RESTORE PRV_PP
0000 ENDIF
0001 CSR_1_CTR_START_BIT: equ 0x01 ; CTR Control register start bit
0001 CSR_1_PWM_START_BIT: equ 0x01 ; PWM Control register start bit
0001 CSR_1_CMP_START_BIT: equ 0x01 ; CMP CR2 register start bit
00E1 CSR_1_SCAN_INT_REG: equ 0x0e1
0001 CSR_1_SCAN_INT_MASK: equ 0x01
0000
0001 CSR_1_Method: equ 1
0000 CSR_1_Method_Freq: equ 0
0001 CSR_1_Method_Period: equ 1
0000
0000 ;--------------------------------------------------
0000 ; Constants for CSR_1 API's
0000 ;--------------------------------------------------
0001 CSR_1_SCAN_CONTINUOUS: equ 0x01
0000 CSR_1_SCAN_ONCE: equ 0x00
0000
0010 CSR_1_SCAN_ACTIVE: equ 0x10 ; Set when scanning is active
0020 CSR_1_SCAN_SET_COMPLETE: equ 0x20 ; Set each time a set of keys is scanned.
0000
0007 CSR_1_ButtonCount: equ 0x7
0000 CSR_1_SliderCount: equ 0x0
0007 CSR_1_TotalSwitchCount: equ 0x7
0000
0000 CSR_1_DAC_LOW: equ 0x00
0001 CSR_1_DAC_HIGH: equ 0x01
0000
0000 CSR_1_ESD_DETECTION: equ 0x0
0007 CSR_1_BUTTONS_EXIST: equ 0x7
0000 CSR_1_SLIDERS_EXIST: equ 0x0
0000
0000 ;--------------------------------------------------
0000 ; Registers Address Constants for CSR_1
0000 ;--------------------------------------------------
0000
0020 CSR_1_PWM_FUNC_REG: equ 0x20 ; PWM Function Reg
0021 CSR_1_PWM_IN_REG: equ 0x21 ; PWM Input Reg
0022 CSR_1_PWM_OUT_REG: equ 0x22 ; PWM Output Reg
0020 CSR_1_PWM_COUNTER_REG: equ 0x20 ; PWM Counter Reg
0021 CSR_1_PWM_PERIOD_REG: equ 0x21 ; PWM Period Reg
0022 CSR_1_PWM_COMPARE_REG: equ 0x22 ; PWM Compare Reg
0023 CSR_1_PWM_CONTROL_REG: equ 0x23 ; PWM Control Reg
0000
0072 CSR_1_ACE_CONTROL1_REG: equ 0x72 ; PWM Function Register
0073 CSR_1_ACE_CONTROL2_REG: equ 0x73 ; PWM Function Register
0000
0024 CSR_1_CTR_COUNTER_LSB_REG: equ 0x24 ; CTR LSB Counter Reg
0025 CSR_1_CTR_PERIOD_LSB_REG: equ 0x25 ; CTR LSB Period Reg
0026 CSR_1_CTR_COMPARE_LSB_REG: equ 0x26 ; CTR LSB Compare Reg
0027 CSR_1_CTR_CONTROL_LSB_REG: equ 0x27 ; CTR LSB Control Reg
0024 CSR_1_CTR_FUNC_LSB_REG: equ 0x24 ; CTR LSB Function Reg
0025 CSR_1_CTR_INPUT_LSB_REG: equ 0x25 ; CTR LSB Input Reg
0026 CSR_1_CTR_OUTPUT_LSB_REG: equ 0x26 ; CTR LSB Output Reg
0000
0028 CSR_1_CTR_COUNTER_MSB_REG: equ 0x28 ; CTR MSB Counter Reg
0029 CSR_1_CTR_PERIOD_MSB_REG: equ 0x29 ; CTR MSB Period Reg
002A CSR_1_CTR_COMPARE_MSB_REG: equ 0x2a ; CTR MSB Compare Reg
002B CSR_1_CTR_CONTROL_MSB_REG: equ 0x2b ; CTR MSB Control Reg
0028 CSR_1_CTR_FUNC_MSB_REG: equ 0x28 ; CTR MSB Function Reg
0029 CSR_1_CTR_INPUT_MSB_REG: equ 0x29 ; CTR MSB Input Reg
002A CSR_1_CTR_OUTPUT_MSB_REG: equ 0x2a ; CTR MSB Output Reg
0000
0000
0000 DR_OFFSET: equ 0x00
0000 DM0_OFFSET: equ 0x00 ; Bank 1
0001 DM1_OFFSET: equ 0x01 ; Bank 1
0003 DM2_OFFSET: equ 0x03 ; Bank 0
00D8 MUX_OFFSET: equ MUX_CR0 ; Bank 1
0000
0000 ;--------------------------------------------------
0000 ; CSR_1 Macro 'Functions'
0000 ;--------------------------------------------------
0000
0000 macro CSR_1_Start_M
0000 or reg[CSR_1_CTR_CONTROL_LSB_REG], CSR_1_CTR_START_BIT
0000 or reg[CSR_1_PWM_CONTROL_REG], CSR_1_PWM_START_BIT
0000 macro CSR_1_Start_Counter_M
0000 or reg[CSR_1_CTR_CONTROL_LSB_REG], CSR_1_CTR_START_BIT
0000 macro CSR_1_Start_CMP_M
0000 mov reg[CSR_1_ACE_CONTROL2_REG], CSR_1_CMP_START_BIT
0000 macro CSR_1_Stop_M
0000 and reg[CSR_1_PWM_CONTROL_REG], ~CSR_1_PWM_START_BIT
0000 and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0000 macro CSR_1_Stop_Counter_M
0000 and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0000 macro CSR_1_Stop_CMP_M
0000 mov reg[CSR_1_ACE_CONTROL2_REG], ~CSR_1_CMP_START_BIT
0000 macro CSR_1_EnableInt_M
0000 M8C_EnableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
0000 macro CSR_1_DisableInt_M
0000 M8C_DisableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
export _CSR_1_bUpdateBaseline
export CSR_1_bUpdateBaseline
IF CSR_1_SLIDERS_EXIST
export _CSR_1_bGetCentroidPos
export CSR_1_bGetCentroidPos
ENDIF
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
AREA InterruptRAM (RAM, REL, CON)
; Global variables
0000 _CSR_1_iaSwBaseline: ; Baseline, one entry for each switch
0000 CSR_1_iaSwBaseline: BLK (2*CSR_1_TotalSwitchCount)
000E _CSR_1_iaSwDiff: ; ABS Diff of raw and and baseline, one entry for each switch
000E CSR_1_iaSwDiff: BLK (2*CSR_1_TotalSwitchCount)
001C _CSR_1_baBtnFThreshold: ; Containing variable finger threshold for each button
001C CSR_1_baBtnFThreshold: BLK CSR_1_ButtonCount
0023 _CSR_1_baSwOnMask: ; Switch mask array containing on/off state of switches
0023 CSR_1_baSwOnMask: BLK ((CSR_1_TotalSwitchCount-1)/8)+1
0024 _CSR_1_bBaselineUpdateTimer: ; Adjusts baseline when signal is within noise threshold
0024 CSR_1_bBaselineUpdateTimer: BLK 1
0025 _CSR_1_fIsBLValid: ; Flag if baseline is valid
0025 CSR_1_fIsBLValid: BLK 1
0026
IF CSR_1_ESD_DETECTION
; ESD variables used for finger detection
_CSR_1_iaSwDeriv: ; Derivative of raw, one entry for each switch
CSR_1_iaSwDeriv: BLK (2*CSR_1_TotalSwitchCount)
_CSR_1_iaSwPrevResult: ; Previous raw result, one entry for each switch
CSR_1_iaSwPrevResult: BLK (2*CSR_1_TotalSwitchCount)
_CSR_1_baESDDebounce: ; Array containing invalid raw data counter to reinstate BL
CSR_1_baESDDebounce: BLK CSR_1_TotalSwitchCount
_CSR_1_baBaselineResetCounter: ; Containing count to update baseline on finger press on startup
CSR_1_baBaselineResetCounter: BLK CSR_1_TotalSwitchCount
_CSR_1_bAbnormalTimer: ; If an ESD event occurs, this timer prevents button presses
CSR_1_bAbnormalTimer: BLK 1
ENDIF
IF CSR_1_SLIDERS_EXIST
; Global slider variables
_CSR_1_baCtrdStartPos: ; Array containing centroid starting position
CSR_1_baCtrdStartPos: BLK CSR_1_SliderCount
_CSR_1_baCtrdSize: ; Array containing centroid size
CSR_1_baCtrdSize: BLK CSR_1_SliderCount
_CSR_1_baCtrdPkPos: ; Array containing peak position of centroid
CSR_1_baCtrdPkPos: BLK CSR_1_SliderCount
_CSR_1_iaCtrdPkValue: ; Array containing peak value of centroid
CSR_1_iaCtrdPkValue: BLK (2*CSR_1_SliderCount)
ENDIF
; Local variables
0026 _CSR_1_bEndOfArray: ; Temp pointer variable
0026 CSR_1_bEndOfArray: BLK 1
0027 _CSR_1_bDivBtwSw: ; Temp divisions between switches
0027 CSR_1_bDivBtwSw: BLK 1
0028 _CSR_1_fIsPressed: ; Temp variable for if any switch is pressed
0028 CSR_1_fIsPressed: BLK 1
0029 _CSR_1_bCurPos: ; Temp position variable
0029 CSR_1_bCurPos: BLK 1
002A _CSR_1_bCurPosMask: ; Temp switch mask used in UpdateBaseline
002A CSR_1_bCurPosMask: BLK 1
002B _CSR_1_bSwMaskPtr: ; Temp switch mask pointer used in UpdateBaseline
002B CSR_1_bSwMaskPtr: BLK 1
002C _CSR_1_bStartIndex: ; Temp Start index
002C CSR_1_bStartIndex: BLK 1
002D
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