easylight.v

easydetect程序

//-----------easylight.v---------------//

module easylight(clk,clr,timex,timey,mode,reset,tout,hg,hr,lg,lr);
input clk,clr,mode,reset;
output [7:0] timex,timey,tout;
output hg,hr,lg,lr;
reg [7:0] timex,timey,tout;
reg mark,hg,hr,lg,lr;

//--------------------------------------------------//
always @(posedge clk or negedge reset)
begin
    if(!reset)  begin   timex<=32;    timey<=16;    end
    else        
        casex(mode)
        0:    if(timex[7:4]==9 && timex[3:0]==9)   timex<=32;
              else   if(timex[3:0]==9) 
                     begin timex[3:0]<=0; timex[7:4]<=timex[7:4]+1; end
                     else timex[3:0]<=timex[3:0]+1;
        1:    if(timey[7:4]==3 && timey[3:0]==9)   timex<=16;
              else   if(timey[3:0]==9) 
                     begin timey[3:0]<=0; timey[7:4]<=timey[7:4]+1; end
                     else timey[3:0]<=timey[3:0]+1;
        endcase
end

//--------------------------------------------------//
always @(posedge clk or negedge clr)
begin
    if(!clr)
    begin   tout<=timex;    mark<=1;    end
    
    else
    begin
         if(tout==1 && mark)     
               begin tout<=timey;  mark<=0;  end
         else if(tout==1 && !mark)
               begin tout<=timex;  mark<=1;  end  
               else
               begin 
               if(tout[3:0]==0)
               begin tout[3:0]<=9;  tout[7:4]<=tout[7:4]-1;   end
               else tout[3:0]<=tout[3:0]-1;
               end
        
    end
end
//--------------------------------------------------//
always @(tout)
begin
    if( (mark && tout>5))
    begin hg<=1; hr<=0; lg<=0; lr<=1;  end
    else if(mark && tout<=5 && tout>=1)
         begin hg<=!clk; hr<=0; lg<=0; lr<=1;  end
    else if(!mark && tout>5)
         begin hg<=0; hr<=1; lg<=1; lr<=0;  end
    else if(!mark && tout<=5 && tout>=1)
         begin hg<=0; hr<=!clk; lg<=1; lr<=0;  end
    else if(tout==0)
         begin hg<=0; hr<=0; lg<=0; lr<=0;  end
end
endmodule