📄 mfucfunc.lst
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C51 COMPILER V4.01, MFUCFUNC 19/08/04 14:33:23 PAGE 1
DOS C51 COMPILER V4.01, COMPILATION OF MODULE MFUCFUNC
OBJECT MODULE PLACED IN D:\13505B\105B\MFUCFUNC.OBJ
COMPILER INVOKED BY: C:\COMP51\C51.EXE D:\13505B\105B\MFUCFUNC.C DB SB OE
stmt level source
1 #include <string.h>
2 #include <intrins.h>
3 #include <MfRc500.h>
4 #include <PcdShare.h>
5 #include <RcComm.h>
6 #include <PcdUtils.h>
7 #include <MfErrNo.h>
8
9 #include "Hardware.h"
10 #include "MfReg.h"
11
12 //unsigned char MSndBuffer[MAX_RF_BUF_SIZE];// = 0; ///< pointer to the transmit buffer
13 //unsigned char MRcvBuffer[MAX_RF_BUF_SIZE];// = 0; ///< pointer to the receive buffer
14 //volatile unsigned char * MSndBuffer;// = 0; ///< pointer to the transmit buffer
15 volatile unsigned char * MRcvBuffer;// = 0; ///< pointer to the receive buffer
16
17 volatile MfCmdInfo MInfo;
18
19 unsigned char idata MLastSelectedSnr[5];
20 unsigned char idata RicRxTxBuffer[26]; // idata
21 extern uchar Block_Index; //test 202.11.26
22
23 #define TCLFSDSNDMAX 8 ///< max. frame size send
24 #define TCLFSDRECMAX 8 ///< max. frame size rcv
25 #define TCLDSMAX 3 ///< max. baudrate divider PICC --> PCD
26 #define TCLDRMAX 3 ///< max. baudrate divider PCD --> PICC
27
28 #define TCLDSDFLT 0 ///< default baudrate divider PICC --> PCD
29 #define TCLDRDFLT 0 ///< default baudrate divider PCD --> PICC
30
31
32 char Mf500PcdConfig(void);
33 char Mf500ActiveAntennaSlaveConfig(void);
34 char Mf500ActiveAntennaMasterConfig(void);
35 char Mf500PiccRequest(unsigned char req_code, // request code ALL = 0x52
36 // or IDLE = 0x26
37 unsigned char *atq); // answer to request
38 char Mf500PiccCommonRequest(unsigned char req_code,
39 unsigned char *atq);
40 char Mf500PiccAnticoll (unsigned char bcnt,
41 unsigned char *snr);
42 char Mf500PiccCascAnticoll (unsigned char select_code,
43 unsigned char bcnt,
44 unsigned char *snr);
45 char Mf500PiccSelect(unsigned char *snr,
46 unsigned char *sak);
47 char Mf500PiccCascSelect(unsigned char select_code,
48 unsigned char *snr,
49 unsigned char *sak);
50 char Mf500PiccActivateIdle(unsigned char br,
51 unsigned char *atq,
52 unsigned char *sak,
53 unsigned char *uid,
54 unsigned char *uid_len);
55 char Mf500PiccActivateWakeup(unsigned char br,
56 unsigned char *atq,
57 unsigned char *sak,
58 unsigned char *uid,
59 unsigned char uid_len);
C51 COMPILER V4.01, MFUCFUNC 19/08/04 14:33:23 PAGE 2
60 char Mf500PiccAuth(unsigned char key_type, // PICC_AUTHENT1A or PICC_AUTHENT1B
61 unsigned char key_addr, // key address in reader storage
62 unsigned char block); // block number which should be
63 // authenticated
64 char Mf500PiccAuthE2( unsigned char auth_mode, // PICC_AUTHENT1A or PICC_AUTHENT1B
65 unsigned char *snr, // 4 bytes card serial number
66 unsigned char key_sector, // 0 <= key_sector <= 15
67 unsigned char block); // 0 <= block <= 256
68 char Mf500HostCodeKey( unsigned char *uncoded, // 6 bytes key value uncoded
69 unsigned char *coded); // 12 bytes key value coded
70 char Mf500PiccAuthKey( unsigned char auth_mode,
71 unsigned char *snr,
72 unsigned char *keys,
73 unsigned char block);
74 char Mf500PcdLoadKeyE2(unsigned char key_type,
75 unsigned char sector,
76 unsigned char *uncoded_keys);
77 char Mf500PiccAuthState( unsigned char auth_mode,
78 unsigned char *snr,
79 unsigned char block);
80
81 char Mf500PiccRead( unsigned char addr,
82 unsigned char * DataTemp);
83 char Mf500PiccWrite( unsigned char addr,
84 unsigned char *DataTemp);
85 char Mf500PiccValue(unsigned char dd_mode,
86 unsigned char addr,
87 unsigned char *value,
88 unsigned char trans_addr);
89 char Mf500PiccValueDebit(unsigned char dd_mode,
90 unsigned char addr,
91 unsigned char *value);
92 char Mf500PiccHalt(void);
93 char Mf500PcdSetDefaultAttrib(void);
94 char Mf500PiccExchangeBlock(unsigned char *send_data,
95 unsigned char send_bytelen,
96 unsigned char *rec_data,
97 unsigned char *rec_bytelen,
98 unsigned char append_crc,
99 unsigned long timeout );
100
101 char Mf500LoadConfig(void);
102 //////////////////////////////////////////////////////////////////////
103 // S E T D E F A U L T C O M M A T T R I B S
104 ///////////////////////////////////////////////////////////////////////
105 char Mf500PcdSetDefaultAttrib(void)
106 {
107 1 //char status = MI_OK;
108 1 //Mf500ActiveAntennaMasterConfig();
109 1 //WriteRC(RegControl,0x00);//////////by allen
110 1 //WriteRC(RegTxControl,0x10);
111 1 //WriteRC(RegMfOutSelect,0x00);
112 1 return MI_OK;
113 1 }
114
115
116 ///////////////////////////////////////////////////////////////////////
117 // M I F A R E M O D U L E C O N F I G U R A T I O N
118 ///////////////////////////////////////////////////////////////////////
119 /*char Mf500LoadConfig(void)
120 {
121 char status = MI_OK;
122 unsigned char code InitRegValue[32]={
123 0x00,0x58,0x3f,0x3f,0x19,0x13,0x00,0x00,
124 0x00,0x73,0x08,0xad,0xff,0x00,0x41,0x00,
125 0x00,0x06,0x03,0x63,0x63,0x00,0x00,0x00,
C51 COMPILER V4.01, MFUCFUNC 19/08/04 14:33:23 PAGE 3
126 0x00,0x08,0x07,0x06,0x0a,0x02,0x00,0x00
127 };
128
129 FlushFIFO(); // empty FIFO
130 ResetInfo(MInfo);
131 MRcvBuffer[0]=0x10; // addr low byte
132 MRcvBuffer[1]=0x00; // addr high byte
133
134 memcpy(MRcvBuffer+2,InitRegValue,32);
135
136 MInfo.nBytesToSend=34;
137
138 status = PcdSingleResponseCmd(PCD_WRITEE2,
139 MRcvBuffer,
140 MRcvBuffer,
141 &MInfo); // write e2
142 return status;
143
144 } */
145 /********************************************************************
146 /* Mf500PcdConfig *
147 ********************************************************************/
148 char Mf500PcdConfig(void)
149 {
150 1 char status = MI_RESETERR;
151 1 unsigned short RstLoopCnt = 0;
152 1 unsigned short CmdWaitCnt = 0;
153 1
154 1 // global initialisation
155 1 MRcvBuffer = RicRxTxBuffer; // initialise send buffer
156 1 MRcvBuffer = RicRxTxBuffer; // initialise receive buffer
157 1
158 1 status = PcdReset(); ///////////////////
159 1
160 1 if (status == MI_OK)
161 1 {
162 2
163 2 // test clock Q calibration - value in the range of 0x46 expected
164 2 WriteRC(RegClockQControl,0x0);
165 2 WriteRC(RegClockQControl,0x40);
166 2 // SleepUs(24); // wait approximately 100 us - calibration in progress
167 2 SleepMs(1);
168 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
169 2 // further calibration
170 2
171 2 // The following values for RegBitPhase and
172 2 // RegRxThreshold represents an optimal
173 2 // value for our demo package. For user
174 2 // implementation some changes could be
175 2 // necessary
176 2 // initialize bit phase
177 2 WriteRC(RegBitPhase,0xad);//0xad
178 2
179 2 // initialize minlevel
180 2 WriteRC(RegRxThreshold,0xff);//0xff YinHan
181 2
182 2 // disable auto power down
183 2 WriteRC(RegRxControl2,0x01);//0x01
184 2
185 2 // Depending on the processing speed of the
186 2 // operation environment, the waterlevel
187 2 // can be adapted. (not very critical for
188 2 // mifare applications)
189 2 // initialize waterlevel to value 4
190 2 WriteRC(RegFIFOLevel,0x1a); // initialize to 26d//0x1a
191 2
C51 COMPILER V4.01, MFUCFUNC 19/08/04 14:33:23 PAGE 4
192 2 //Timer Konfiguration
193 2 WriteRC(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=0,////////0x02
194 2 // TStartTxEnd=1,TStartTxBeg=0
195 2 // timer must be stopped manually
196 2
197 2 WriteRC(RegIRqPinConfig,0x02); //delete allen 6.06 interrupt active low enable//03
198 2
199 2 WriteRC(RegRxWait,0x06);// WriteRC(RegRxWait,0x06); change for YinHan
200 2 //WriteRC(RegCwConductance,0xf0);//////////by allen
201 2 //WriteRC(RegTxControl,0x53);
202 2 //WriteRC(RegMfOutSelect,0x00);
203 2 PcdRfReset(10);//10ms // Rf - reset and enable output driver
204 2
205 2 }
206 1
207 1 return status;
208 1 }
209
210 ///////////////////////////////////////////////////////////////////////
211 // M I F A R E R E M O T E A N T E N N A
212 // Configuration of slave module
213 ///////////////////////////////////////////////////////////////////////
214 /*char Mf500ActiveAntennaSlaveConfig(void)
215 {
216 char status = MI_OK;
217
218 FlushFIFO(); // empty FIFO
219 ResetInfo(MInfo);
220 MRcvBuffer[0] = 0x10; // addr low byte
221 MRcvBuffer[1] = 0x00; // addr high byte
222
223 MRcvBuffer[2] = 0x00; // Page
224 MRcvBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
225 MRcvBuffer[4] = 0x3F; // RegCwConductance
226 MRcvBuffer[5] = 0x3F; // RFU13
227 MRcvBuffer[6] = 0x19; // RFU14
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