📄 pcdutils.lst
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178 2 default:
179 2 status = MI_UNKNOWN_COMMAND;
180 2 }
181 1 if (status == MI_OK)
182 1 {
183 2 // Initialize uC Timer for global Timeout management
184 2 ////////////////////////////////////////////////////////////////////
185 2 irqEn|=0x20; // always enable timout irq /////allen 10.23
186 2 waitFor|=0x20; // always wait for timeout///delete it
187 2
188 2 WriteRC(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled // count up from 1
189 2
190 2 WriteRC(RegCommand,cmd); //start command
191 2
C51 COMPILER V4.01, PCDUTILS 19/08/04 14:33:22 PAGE 4
192 2 // wait for commmand completion
193 2 // a command is completed, if the corresponding interrupt occurs
194 2 // or a timeout is signaled
195 2
196 2 TimeOutCount=14049; //change from 4049
197 2 while (!(MpIsrInfo->irqSource & waitFor
198 2 || !TimeOutCount)) // wait for cmd completion or timeout
199 2 {
200 3 TimeOutCount--;
201 3 }
202 2
203 2 WriteRC(RegInterruptEn,0x7F); // disable all interrupts
204 2 WriteRC(RegInterruptRq,0x7F); // clear all interrupt requests
205 2 SetBitMask(RegControl,0x04); // stop timer now
206 2
207 2 WriteRC(RegCommand,PCD_IDLE); // reset command register
208 2
209 2 //Temp=ReadRC(RegFIFOLength);
210 2 //Temp=ReadRC(RegFIFOData);
211 2
212 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
213 2 { // timer 3 expired
214 3 status = MI_ACCESSTIMEOUT;
215 3 }
216 2 else
217 2 status = MpIsrInfo->status; // set status
218 2
219 2 if (status == MI_OK) // no timeout error occured
220 2 {
221 3 if ((tmpStatus = (ReadRC(RegErrorFlag) & 0x17))) // error occured
222 3 {
223 4 if (tmpStatus & 0x01) // collision detected
224 4 {
225 5 info->collPos = ReadRC(RegCollPos); // read collision position
226 5 status = MI_COLLERR;
227 5 }
228 4 else
229 4 {
230 5 info->collPos = 0;
231 5 if (tmpStatus & 0x02) // parity error
232 5 {
233 6 status = MI_PARITYERR;
234 6 }
235 5 }
236 4 if (tmpStatus & 0x04) // framing error
237 4 {
238 5 status = MI_FRAMINGERR;
239 5 }
240 4 if (tmpStatus & 0x10) // FIFO overflow
241 4 {
242 5 FlushFIFO();
243 5 status = MI_OVFLERR;
244 5 }
245 4 if (tmpStatus & 0x08) // CRC error
246 4 {
247 5 status = MI_CRCERR;
248 5 }
249 4 if (status == MI_OK)
250 4 status = MI_NY_IMPLEMENTED;
251 4 // key error occures always, because of
252 4 // missing crypto 1 keys loaded
253 4 }
254 3 // if the last command was TRANSCEIVE, the number of
255 3 // received bits must be calculated - even if an error occured
256 3 if (cmd == PCD_TRANSCEIVE || cmd == PCD_RECEIVE)
257 3 {
C51 COMPILER V4.01, PCDUTILS 19/08/04 14:33:22 PAGE 5
258 4 // number of bits in the last byte
259 4 lastBits = ReadRC(RegSecondaryStatus) & 0x07;
260 4 if (lastBits)
261 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
262 4 else
263 4 info->nBitsReceived += info->nBytesReceived * 8;
264 4 }
265 3 }
266 2 else
267 2 {
268 3 info->collPos = 0x00;
269 3 }
270 2 }
271 1
272 1 // READER_INT_DISABLE;
273 1
274 1 //PcdIsrFct = EmptyPcdIsrFct; // reset the ISR-Function pointer to
275 1 // an empty function body
276 1 // do this before clearing the Mp XXXX variables
277 1 CloseExternInt0();
278 1 MpIsrInfo = 0; // reset interface variables for ISR
279 1 MpIsrOut = 0;
280 1 MpIsrIn = 0;
281 1 return status;
282 1 }
283
284 ///////////////////////////////////////////////////////////////////////////////
285 // Interrupt Handler RIC
286 ///////////////////////////////////////////////////////////////////////////////
287 void SingleResponseIsr(void)
288 {
289 1 unsigned char irqBits; //static
290 1 unsigned char irqMask;
291 1 unsigned char oldPageSelect;
292 1 unsigned char nbytes;
293 1 unsigned char cnt;
294 1
295 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
296 1 // correctly
297 1 {
298 2 oldPageSelect = ReadRawRC(RegPage); // save old page select
299 2 // Attention: ReadRC cannnot be
300 2 // used because of the internal
301 2 // write sequence to the page
302 2 // reg
303 2 WriteRawRC(RegPage,0x80); // select page 0 for ISR
304 2 while( (ReadRawRC(RegPrimaryStatus) & 0x08)) // loop while IRQ pending
305 2 {
306 3 irqMask = ReadRawRC(RegInterruptEn); // read enabled interrupts
307 3 // read pending interrupts
308 3 irqBits = ReadRawRC(RegInterruptRq) & irqMask;
309 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
310 3 //************ LoAlertIRQ ******************
311 3 if (irqBits & 0x01) // LoAlert
312 3 {
313 4 nbytes = MFIFOLength - ReadRawRC(RegFIFOLength);
314 4 // less bytes to send, than space in FIFO
315 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
316 4 {
317 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
318 5 WriteRawRC(RegInterruptEn,0x01); // disable LoAlert IRQ
319 5 }
320 4 // write remaining data to the FIFO
321 4 for ( cnt = 0;cnt < nbytes;cnt++)
322 4 {
323 5 WriteRawRC(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
C51 COMPILER V4.01, PCDUTILS 19/08/04 14:33:22 PAGE 6
324 5 MpIsrInfo->nBytesSent++;
325 5 }
326 4 WriteRawRC(RegInterruptRq,0x01); // reset IRQ bit
327 4 }
328 3
329 3 //************* TxIRQ Handling **************
330 3 if (irqBits & 0x10) // TxIRQ
331 3 {
332 4 WriteRawRC(RegInterruptRq,0x10); // reset IRQ bit
333 4 WriteRawRC(RegInterruptEn,0x82); // enable HiAlert Irq for
334 4 // response
335 4 if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
336 4 { // switch off parity generation
337 5 WriteRC(RegChannelRedundancy,0x02); // RxCRC and TxCRC disable, parity disable
338 5 WriteRawRC(RegPage,0x00); // reset page address
339 5 }
340 4 }
341 3
342 3 //************* HiAlertIRQ or RxIRQ Handling ******************
343 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
344 3 {
345 4 // read some bytes ( length of FIFO queue)
346 4 // into the receive buffer
347 4 nbytes = ReadRawRC(RegFIFOLength);
348 4 // read date from the FIFO and store them in the receive buffer
349 4 for ( cnt = 0; cnt < nbytes; cnt++)
350 4 {
351 5 MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawRC(RegFIFOData);
352 5 MpIsrInfo->nBytesReceived++;
353 5 }
354 4 WriteRawRC(RegInterruptRq,0x0A & irqBits);
355 4 // reset IRQ bit - idle irq will
356 4 // be deleted in a seperate section
357 4 }
358 3
359 3 //************** IdleIRQ Handling ***********
360 3 if (irqBits & 0x04) // Idle IRQ
361 3 {
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