📄 aal5_sar.c
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* Frames_to_xmit = pattern.
*
* PARAMETERS: none
*
* RETURNS: none
*
*-----------------------------------------------------------------------------*/
void InitBuffers()
{
UWORD i;
UBYTE *ptr_rcv, *ptr_xmit;
/*-----------------------------------------------------*/
/* Initialize the Receive and Transmit Buffer pointers */
/*-----------------------------------------------------*/
Received_frames = (UBYTE *)RX_BUFF_ADDR;
Frames_to_xmit = (UBYTE *)TX_BUFF_ADDR;
Raw_cells = (UBYTE *)RAW_CELL_RX_BUFF_ADDR;
ptr_rcv = (UBYTE *)Received_frames;
ptr_xmit = (UBYTE *)Frames_to_xmit;
/*******************************************/
/* Initialize the Receive Buffers with */
/* zero (clear the buffers). */
/*******************************************/
memset(ptr_rcv, 0, FRAME_LENGTH*NUM_FRAMES);
/*******************************************/
/* Initialize the Transmit Buffers with */
/* the transmit pattern. */
/*******************************************/
for(i = 0; i < NUM_FRAMES; i++)
{
memset(ptr_xmit, i+1, FRAME_LENGTH);
ptr_xmit += FRAME_LENGTH;
}
/*******************************************/
/* Initialize the raw cell Receive buffers */
/*******************************************/
ptr_rcv = (UBYTE *)Raw_cells;
memset(ptr_rcv, 0, NUM_RAW_CELL_BUFFS*RAW_CELL_BUFF_SIZE);
} /* end of InitBuffers */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: SCC_init
*
*
* DESCRIPTION:
*
* SCCx AAL5 ATM Initialization Routine.
*
* EXTERNAL EFFECT:
*
* Parameter RAM and various registers on the 860 including interrupt related
* registers and port registers. This function, when complete,
*
* PARAMETERS: None
*
* RETURNS: None
*
*----------------------------------------------------------------------------*/
void SCC_init()
{
UHWORD mask1;
UWORD mask2;
UWORD i = 0;
/*---------------------------------------------*/
/* Configure Port A to enable TXDx & RXDx (i.e.*/
/* transmit and receive data pins for SCCx. */
/*---------------------------------------------*/
/* Enable RX & TX pins in PORT A */
mask1 = 0x3;
IMMR->pio_padir &= ~(mask1 << (2*SCC_num));
IMMR->pio_papar |= (mask1 << (2*SCC_num));
/*---------------------------------------------*/
/* Enable ATM functionality and RX & TX pins */
/* via PORT D. */
/*---------------------------------------------*/
IMMR->pio_pdpar |= 0x8000;
/*---------------------------------------------*/
/* Make sure Port C is initialized to 0 */
/*---------------------------------------------*/
IMMR->pio_pcdir = 0;
IMMR->pio_pcpar = 0;
IMMR->pio_pcso = 0;
IMMR->pio_pcint = 0;
/*----------------------------------------------------------*/
/* Enable Baud rate generator and the BRG Clock Prescaler */
/* Divide by 16 option. At 24 Mhz, which is the assumed */
/* ADS operating frequency, the baud rate is 24 Mhz/16, or */
/* 1.5 Mbps. */
/* */
/* NOTE: The baud rate must be greater or equal to the */
/* rate at which the APC schedules cells. APC Overrun ex- */
/* ceptions will result if the BRG is lower than the APC */
/* rate. */
/*----------------------------------------------------------*/
IMMR->brgc4 = 0x00010001;
/*---------------------------------------------------------*/
/* Initialize the SI Clock Route Register (SICR). */
/* */
/* - Configure BRG4 as SCCx's transmit and receive clock */
/* source. */
/*---------------------------------------------------------*/
mask2 = 0xFF;
IMMR->si_sicr &= ~(mask2 << (8*SCC_num));
mask2 = 0x1B;
IMMR->si_sicr |= (mask2 << (8*SCC_num));
/********************************************************/
/* SCCx (ATM Protocol) Parameter RAM Initialization */
/********************************************************/
/*----------------------------------------*/
/* Set SRFCR,STFCR -- Rx,Tx Function Code */
/*----------------------------------------*/
IMMR->PRAM[SCC_num].sar.srfcr = 0x18; /* Normal Operation and Motorola
byte ordering (i.e. Big Endian) */
IMMR->PRAM[SCC_num].sar.stfcr = 0x18; /* Motorola byte ordering, Normal
access */
/*---------------------------------------------*/
/* Set STSTATE,SRSTATE -- Rx,Tx control/state */
/*---------------------------------------------*/
IMMR->PRAM[SCC_num].sar.ststate = 0x02; /* Configure a max of 32 channels
and serial mode operation */
IMMR->PRAM[SCC_num].sar.srstate = 0x02; /* Configure a max of 32 channels
and serial mode operation */
/*-------------------------------------------------*/
/* Initialize the MRBLR and SMRBLR. MRBLR must be */
/* initialized to zero and SMRBLR is initialized */
/* to the size of the receive buffer. */
/* */
/* SMRBLR must be a multiple of 48 bytes. */
/*-------------------------------------------------*/
IMMR->PRAM[SCC_num].sar.mrblr = 0;
IMMR->PRAM[SCC_num].sar.smrblr = ((NUM_FRAMES * FRAME_LENGTH)%48) ?
((((NUM_FRAMES * FRAME_LENGTH)/48) +1)
* 48) : NUM_FRAMES * FRAME_LENGTH;
/*------------------------------------------------------*/
/* Initialize the receive and transmit state parameters.*/
/* The 1st byte must equal that of SRFCR and STFCR res- */
/* pectively and the remaining 3 bytes must be zero. */
/*------------------------------------------------------*/
IMMR->PRAM[SCC_num].sar.rstate = ((UWORD)
(IMMR->PRAM[SCC_num].sar.srfcr)) << 24;
IMMR->PRAM[SCC_num].sar.tstate = ((UWORD)
(IMMR->PRAM[SCC_num].sar.stfcr)) << 24;
/*------------------------------------------------------*/
/* Set the Receive and Transmit Buffer Descriptors Base */
/* address. Note that the SAR BDs reside in external */
/* memory. */
/*------------------------------------------------------*/
IMMR->PRAM[SCC_num].sar.tbdbase = TBD_ADDR;
IMMR->PRAM[SCC_num].sar.rbdbase = RBD_ADDR;
/*--------------------------------------------------------------------*/
/* Configure the start of the receive/transmit connection table. This */
/* is actually the "offset" from dual port RAM where the connection */
/* table begins. */
/*--------------------------------------------------------------------*/
IMMR->PRAM[SCC_num].sar.ctbase = CT_BASE_OFFSET;
IMMR->PRAM[SCC_num].sar.t_cnt = 0;
/*-----------------------------------------------------------------*/
/* Initialize the lookup table parameters. */
/*-----------------------------------------------------------------*/
/* Initialize cell header mask */
IMMR->PRAM[SCC_num].sar.lookup.hmask = 0x0FFFFFF0;/* Use only VPI/VCI when */
/* looking up an entry */
/* Initalize Address Match table base (offset from DPR) */
IMMR->PRAM[SCC_num].sar.lookup.ambase = AM_BASE_OFFSET;
/* Initalize Address Match table end address (offset from DPR) */
IMMR->PRAM[SCC_num].sar.lookup.amend = AM_END_OFFSET;
/* Initalize pointer to the channel Address pointer table (this table */
/* points to the corresponding RCT entry. */
IMMR->PRAM[SCC_num].sar.lookup.apbase = AP_BASE_OFFSET;
/*----------------------------------------------------------*/
/* Initialize Transmit Queue pointers */
/*----------------------------------------------------------*/
/* xmit queue offset from DPR */
IMMR->PRAM[SCC_num].sar.tqbase = XMIT_Q_BASE_OFFSET;
/* xmit queue APC pointer must be initialized to the value of tqbase */
IMMR->PRAM[SCC_num].sar.tqaptr = IMMR->PRAM[SCC_num].sar.tqbase;
/* xmit queue transmitter pointer must be initialized to tqbase */
IMMR->PRAM[SCC_num].sar.tqtptr = IMMR->PRAM[SCC_num].sar.tqbase;
/* end of queue offset (DPR) */
IMMR->PRAM[SCC_num].sar.tqend = XMIT_Q_END_OFFSET;
/*-----------------------------------------------------*/
/* Initialize GSMR_H for ATM transmit/receive. Note */
/* that MRBLR must be set to zero for ATM operation. */
/* */
/* SET: TRX, TTX, CDP, CTSP, CDS, CTSS bits */
/*-----------------------------------------------------*/
IMMR->scc_regs[SCC_num].scc_gsmr_h |= 0x00001F80;
/* Disable cell payload scrambling and HEC coset rules */
/* in the Protocol Specific Mode Register. */
IMMR->scc_regs[SCC_num].scc_psmr = 0x0;
/*-------------------------------------------------------------------*/
/* Reset GSMR_L. */
/*-------------------------------------------------------------------*/
IMMR->scc_regs[SCC_num].scc_gsmr_l = 0;
/*-----------------------------------------*/
/* Clear SCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMMR->scc_regs[SCC_num].scc_scce = ALL_ONES;
/*-------------------------------------------------------*/
/* Enable SCCx Interrupts to the CP Interrupt Controller */
/*-------------------------------------------------------*/
mask2 = CIMR_SCC1;
IMMR->cpmi_cimr = (mask2 >> (1*SCC_num));
/*-----------------------------------------------*/
/* Set Appropriate Interrupt Level Bit in SIMASK */
/*-----------------------------------------------*/
switch(INTERRUPT_LEVEL)
{
case 0:
IMMR->siu_simask = SIMASK_LVM0;
break;
case 1:
IMMR->siu_simask = SIMASK_LVM1;
break;
case 2:
IMMR->siu_simask = SIMASK_LVM2;
break;
case 3:
IMMR->siu_simask = SIMASK_LVM3;
break;
case 4:
IMMR->siu_simask = SIMASK_LVM4;
break;
case 5:
IMMR->siu_simask = SIMASK_LVM5;
break;
case 6:
IMMR->siu_simask = SIMASK_LVM6;
break;
case 7:
IMMR->siu_simask = SIMASK_LVM7;
break;
default:
break; /* Bad value */
} /* end switch */
/*-----------------------------------------------------------------*/
/* Write SCCM to Enable Interrupts. All valid interrupts are */
/* enabled. */
/*-----------------------------------------------------------------*/
IMMR->scc_regs[SCC_num].scc_sccm = 0x1C3F;
/*----------------------------------------------------------------*/
/* Write CICR to Configure SCCx Interrupt Priority Settings: */
/* */
/* SCC Priorities */
/* SCC2 - Highest Priority */
/* IRL0-IRL2 (Interrupt Request Level) = Constant set by user */
/* HP0-HP4 (Highest Priority) = Original Priority */
/* IEN = Enable CPM Interrupts */
/*----------------------------------------------------------------*/
IMMR->cpmi_cicr = 0xE49F80 | (INTERRUPT_LEVEL << 13);
/*-----------------------------------------*/
/* Enable External Interrupts at CPU level */
/*-----------------------------------------*/
#ifdef MetaWare
_ASM(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#else
#ifdef Diab
asm(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#endif
#endif
} /* end SCC_init() */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptInit
*
*
* DESCRIPTION:
*
* Copy Interrupt Handler code from its current address to the specified
* PowerPC Interrupt Vector.
*
* EXTERNAL EFFECTS:
*
* PARAMETERS:
*
* interrupt_vector -- address to which interrupt code should be copied
* interrupt_code -- current address of interrupt code
*
* RETURNS: NONE
*
*-----------------------------------------------------------------------------*/
void InterruptInit(UWORD *interrupt_vector,
UWORD interrupt_code[])
{
UHWORD index;
UWORD *instruction;
UWORD *next_vector;
next_vector = (interrupt_vector + VECTOR_BLOCK_LEN); /* next vector entry */
for(instruction = interrupt_vector, index = 0; instruction < next_vector;
instruction++, index++)
*instruction = interrupt_code[index];
} /* end InterruptInit */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: BDRxError
*
* DESCRIPTION:
*
* Return TRUE if Buffer Descriptor Status bd_cstatus indicates Receive
* Error; Return FALSE otherwise note Receive Errors are as follows:
*
* 0x80: HEC Error
* 0x10: Received Frame was aborted
* 0x2: Overrun (OV)
* 0x1: CRC Error
*
* EXTERNAL EFFECTS: None
*
* PARAMETERS:
*
* bd_cstatus
*
* RETURNS: TRUE if there was an error and FALSE if there wasn't
*
*-----------------------------------------------------------------------------*/
UHWORD BDRxError(UHWORD bd_cstatus)
{
if (bd_cstatus & BD_RX_ERROR)
return TRUE;
else
return FALSE;
} /* end BDRxError */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: LastBD
*
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