__projnav.log

这是非常好的vhdl例子

 Number of Slices:                     211  out of   1920    10%  
 Number of Slice Flip Flops:           159  out of   3840     4%  
 Number of 4 input LUTs:               345  out of   3840     8%  
 Number of bonded IOBs:                 11  out of    141     7%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sysclk                             | BUFGP                  | 53    |
clocknum_count_6:Q                 | NONE                   | 95    |
showdata_hsyncb:Q                  | NONE                   | 11    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.450ns (Maximum Frequency: 408.163MHz)
   Minimum input arrival time before clock: 2.856ns
   Maximum output required time after clock: 6.753ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\work\coreban\submouse/_ngo -uc
top.ucf -p xc3s200-pq208-4 top.ngc top.ngd 

Reading NGO file "e:/work/coreban/submouse/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41872 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s200pq208-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         153 out of   3,840    3%
  Number of 4 input LUTs:             274 out of   3,840    7%
Logic Distribution:
  Number of occupied Slices:                          215 out of   1,920   11%
    Number of Slices containing only related logic:     215 out of     215  100%
    Number of Slices containing unrelated logic:          0 out of     215    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            347 out of   3,840    9%
  Number used as logic:                274
  Number used as a route-thru:          73
  Number of bonded IOBs:               12 out of     141    8%
    IOB Flip Flops:                     6
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  3,999
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  71 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_map.mrp" for details.
Completed process "Map".

Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc3s200-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE



Started process "Place & Route".





Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s200, package pq208, speed -4
Loading device for application Par from file '3s200.nph' in environment
D:/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            12 out of 141     8%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of Slices                  215 out of 1920   11%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989a0d) REAL time: 0 secs 

.
Phase 3.8
..................
Phase 3.8 (Checksum:9aa064) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1187 unrouted;       REAL time: 2 secs 

Phase 2: 1062 unrouted;       REAL time: 3 secs 

Phase 3: 337 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|      sysclk_BUFGP       |  BUFGMUX1| No   |   33 |  0.047     |  0.632      |
+-------------------------+----------+------+------+------------+-------------+
| clocknum_count<6>       |   Local  |      |   58 |  0.364     |  2.340      |
+-------------------------+----------+------+------+------------+-------------+
|   showdata_hsyncb       |   Local  |      |    8 |  0.165     |  2.287      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  61 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sat Oct 23 14:24:20 2004
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
PAR completed successfully



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Started process "Generate Programming File".

Completed process "Generate Programming File".



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