__projnav.log

这是非常好的vhdl例子

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/work/coreban/submouse/Count64.vhd in Library work.
Entity <count64> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/submouse/Mouse.vhd in Library work.
Entity <mouse> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/submouse/Vgacore.vhd in Library work.
Entity <vgacore> (Architecture <vgacore_arch>) compiled.
Compiling vhdl file e:/work/coreban/submouse/Top.vhd in Library work.
Entity <top> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 12: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/submouse/Top.vhd line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <count64> (Architecture <behavioral>).
Entity <count64> analyzed. Unit <count64> generated.

Analyzing Entity <mouse> (Architecture <behavioral>).
Entity <mouse> analyzed. Unit <mouse> generated.

Analyzing Entity <vgacore> (Architecture <vgacore_arch>).
INFO:Xst:1561 - e:/work/coreban/submouse/Vgacore.vhd line 132: Mux is complete : default of case is discarded
INFO:Xst:1561 - e:/work/coreban/submouse/Vgacore.vhd line 143: Mux is complete : default of case is discarded
INFO:Xst:1561 - e:/work/coreban/submouse/Vgacore.vhd line 182: Mux is complete : default of case is discarded
Entity <vgacore> analyzed. Unit <vgacore> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgacore>.
    Related source file is e:/work/coreban/submouse/Vgacore.vhd.
WARNING:Xst:647 - Input <read_data> is never used.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <hsyncb>.
    Found 3-bit register for signal <rgb>.
    Found 10-bit subtractor for signal <$n0010> created at line 170.
    Found 10-bit subtractor for signal <$n0012> created at line 170.
    Found 8-bit adder for signal <$n0027> created at line 170.
    Found 9-bit adder for signal <$n0028> created at line 170.
    Found 9-bit adder for signal <$n0029> created at line 170.
    Found 8-bit adder for signal <$n0030> created at line 170.
    Found 12-bit comparator less for signal <$n0031> created at line 48.
    Found 11-bit comparator less for signal <$n0032> created at line 64.
    Found 3-bit 8-to-1 multiplexer for signal <$n0039>.
    Found 3-bit xor2 for signal <$n0040> created at line 182.
    Found 3-bit xor2 for signal <$n0041> created at line 181.
    Found 3-bit xor2 for signal <$n0042> created at line 180.
    Found 3-bit xor2 for signal <$n0043> created at line 179.
    Found 3-bit xor2 for signal <$n0044> created at line 178.
    Found 11-bit adder for signal <$n0048> created at line 49.
    Found 10-bit adder for signal <$n0049> created at line 65.
    Found 12-bit comparator greatequal for signal <$n0066> created at line 80.
    Found 12-bit comparator lessequal for signal <$n0067> created at line 80.
    Found 11-bit comparator greatequal for signal <$n0068> created at line 96.
    Found 11-bit comparator lessequal for signal <$n0069> created at line 96.
    Found 12-bit comparator greater for signal <$n0070> created at line 112.
    Found 11-bit comparator greater for signal <$n0071> created at line 112.
    Found 12-bit comparator lessequal for signal <$n0072> created at line 157.
    Found 12-bit comparator greatequal for signal <$n0073> created at line 157.
    Found 12-bit comparator lessequal for signal <$n0074> created at line 157.
    Found 11-bit comparator lessequal for signal <$n0075> created at line 157.
    Found 11-bit comparator greatequal for signal <$n0076> created at line 157.
    Found 11-bit comparator lessequal for signal <$n0077> created at line 157.
    Found 11-bit comparator greatequal for signal <$n0078> created at line 170.
    Found 11-bit comparator lessequal for signal <$n0079> created at line 170.
    Found 10-bit subtractor for signal <$n0080> created at line 170.
    Found 10-bit comparator greatequal for signal <$n0081> created at line 170.
    Found 10-bit comparator lessequal for signal <$n0082> created at line 170.
    Found 10-bit subtractor for signal <$n0083> created at line 170.
    Found 10-bit comparator greatequal for signal <$n0084> created at line 170.
    Found 10-bit comparator lessequal for signal <$n0085> created at line 170.
    Found 11-bit comparator greatequal for signal <$n0086> created at line 170.
    Found 11-bit comparator lessequal for signal <$n0087> created at line 170.
    Found 3-bit register for signal <bangcolor>.
    Found 3-bit register for signal <frame>.
    Found 11-bit register for signal <hcnt>.
    Found 3-bit register for signal <hrgb>.
    Found 10-bit register for signal <mousehcnt>.
    Found 10-bit register for signal <mousevcnt>.
    Found 1-bit register for signal <pblank>.
    Found 10-bit register for signal <vcnt>.
    Found 3-bit register for signal <vrgb>.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred  10 Adder/Subtracter(s).
	inferred  22 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <vgacore> synthesized.


Synthesizing Unit <mouse>.
    Related source file is e:/work/coreban/submouse/Mouse.vhd.
WARNING:Xst:646 - Signal <packet_good> is assigned but never used.
WARNING:Xst:646 - Signal <q<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <clean_clk> is never used or assigned.
WARNING:Xst:1780 - Signal <n_rise> is never used or assigned.
WARNING:Xst:1780 - Signal <n_fall> is never used or assigned.
    Register <risesig<0>> equivalent to <fallsig<0>> has been removed
    Found finite state machine <FSM_0> for signal <m2_state>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 29                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | m2_reset                                       |
    | Power Up State     | m2_reset                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <q<6>> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <q<19>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 1-bit tristate buffer for signal <ps2_clk>.
    Found 1-bit tristate buffer for signal <ps2_data>.
    Found 1-bit register for signal <right_button>.
    Found 1-bit register for signal <left_button>.
    Found 10-bit up accumulator for signal <mousex>.
    Found 10-bit up accumulator for signal <mousey>.
    Found 10-bit adder for signal <$n0029> created at line 299.
    Found 11-bit comparator greatequal for signal <$n0037> created at line 311.
    Found 11-bit comparator lessequal for signal <$n0038> created at line 311.
    Found 11-bit comparator greatequal for signal <$n0039> created at line 326.
    Found 11-bit comparator lessequal for signal <$n0040> created at line 326.
    Found 6-bit up counter for signal <bitcount>.
    Found 3-bit register for signal <fallsig>.
    Found 10-bit register for signal <mouseyy>.
    Found 33-bit register for signal <q>.
    Found 2-bit register for signal <risesig<2:1>>.
    Found 9-bit up counter for signal <watchdog_timer_count>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred   2 Accumulator(s).
	inferred  50 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred   2 Tristate(s).
Unit <mouse> synthesized.


Synthesizing Unit <count64>.
    Related source file is e:/work/coreban/submouse/Count64.vhd.
    Found 7-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <count64> synthesized.


Synthesizing Unit <top>.
    Related source file is e:/work/coreban/submouse/Top.vhd.
WARNING:Xst:646 - Signal <error_no_ack> is assigned but never used.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <m2_state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 11
 10-bit adder                      : 2
 11-bit adder                      : 1
 9-bit adder                       : 2
 8-bit adder                       : 2
 10-bit subtractor                 : 4
# Counters                         : 3
 6-bit up counter                  : 1
 7-bit up counter                  : 1
 9-bit up counter                  : 1
# Accumulators                     : 2
 10-bit up accumulator             : 2
# Registers                        : 66
 10-bit register                   : 4
 1-bit register                    : 56
 3-bit register                    : 5
 11-bit register                   : 1
# Comparators                      : 26
 11-bit comparator greatequal      : 6
 11-bit comparator lessequal       : 7
 10-bit comparator lessequal       : 2
 10-bit comparator greatequal      : 2
 12-bit comparator lessequal       : 3
 12-bit comparator greatequal      : 2
 11-bit comparator greater         : 1
 12-bit comparator greater         : 1
 11-bit comparator less            : 1
 12-bit comparator less            : 1
# Multiplexers                     : 2
 3-bit 8-to-1 multiplexer          : 1
 3-bit 2-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2
# Xors                             : 5
 3-bit xor2                        : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <frame_0> (without init value) is constant in block <vgacore>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <frame_1> (without init value) is constant in block <vgacore>.
WARNING:Xst:1291 - FF/Latch <FFd2> is unconnected in block <m2_state>.
WARNING:Xst:1291 - FF/Latch <mousedata_m2_state_FFd2> is unconnected in block <top>.

Optimizing unit <top> ...

Optimizing unit <vgacore> ...
Loading device for application Xst from file '3s200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register mousedata_risesig_1 equivalent to mousedata_fallsig_1 has been removed
Register mousedata_risesig_2 equivalent to mousedata_fallsig_2 has been removed
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 12.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4