top.twr

这是非常好的vhdl例子

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o top.twr
top.pcf


Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc3s400,-4 (ADVANCED 1.29 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock sysclk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
model1<0>   |    5.540(R)|   -2.548(R)|sysclk_BUFGP      |   0.000|
model1<1>   |    5.423(R)|   -2.888(R)|sysclk_BUFGP      |   0.000|
model1<2>   |    5.331(R)|   -2.887(R)|sysclk_BUFGP      |   0.000|
reset1      |    4.046(R)|   -0.577(R)|sysclk_BUFGP      |   0.000|
------------+------------+------------+------------------+--------+

Clock sysclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
hsyncb      |   10.384(R)|sysclk_BUFGP      |   0.000|
rgb<0>      |    7.173(R)|sysclk_BUFGP      |   0.000|
rgb<1>      |    7.173(R)|sysclk_BUFGP      |   0.000|
rgb<2>      |    7.173(R)|sysclk_BUFGP      |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock sysclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sysclk         |   13.456|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Dec 02 09:30:24 2004
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Peak Memory Usage: 59 MB