top.vhd

这是非常好的vhdl例子

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
    Port ( sysclk : in std_logic;
           reset1 : in std_logic;
           ps2clk : inout std_logic;
           ps2data : inout std_logic;
		     hsyncb: buffer std_logic;	-- horizontal (line) sync
		     vsyncb: buffer std_logic;	-- vertical (frame) sync
           model1: in std_logic_vector(2 downto 0); --background color select.
			  --key5 : out std_logic;
			  --key6 : out std_logic;
		     rgb: buffer std_logic_vector(2 downto 0));-- red,green,blue colors));
end top;

architecture Behavioral of top is

signal clk : std_logic;
--signal sysclk_2 : std_logic;--VGA dot clock
--signal div_count : std_logic_vector(1 downto 0);
signal left_button : std_logic;
signal right_button : std_logic;
signal mousex : std_logic_vector(9 downto 0);
signal mousey : std_logic_vector(9 downto 0);
signal error_no_ack : std_logic;
signal read : std_logic;
signal reset : std_logic;
signal model : std_logic_vector(2 downto 0);

--clock ferquence
component count64 
    Port ( sysclk : in std_logic;
           reset : in std_logic;
           clkout : out std_logic);
end component;

--show the data in CRT
component vgacore 
	port
	(
		reset : in std_logic;	-- reset
		clock : in std_logic;	-- VGA dot clock
		hsyncb : buffer std_logic;	-- horizontal (line) sync
		vsyncb : buffer std_logic;	-- vertical (frame) sync
      model : in std_logic_vector(2 downto 0); --background color select.
		rgb : buffer std_logic_vector(2 downto 0);-- red,green,blue colors
		read_data : in std_logic; -----the flag show data is ready to be read
		lbutton : in std_logic;
		rbutton : in std_logic;
		mousex : in std_logic_vector(9 downto 0);
		mousey : in std_logic_vector(9 downto 0)  ------mouse data
);
end component;

--mouse data receive
component mouse    
    Port (
	       clk : in std_logic;
          reset : in std_logic;
          ps2_clk : inout std_logic;
          ps2_data : inout std_logic;
          left_button : out std_logic;
          right_button : out std_logic;
          mousex : out std_logic_vector(9 downto 0);
          mousey : out std_logic_vector(9 downto 0);
          data_ready : out std_logic;-- rx_read_o
          --read : in std_logic; -- rx_read_ack_i
          error_no_ack : out std_logic
			 );
end component;

begin

  --A: process (reset,sysclk)
  --begin
    --if (reset='1') then
     -- div_count <= "00";
    --elsif (sysclk'event and sysclk='1') then
     -- div_count <= div_count+'1';
    --end if;
  --end process;
  --B: sysclk_2 <= div_count(1);

  --reset <= resn; --
  --key5 <= '0';
  --key6 <= '0';

  reset<=not reset1;
  model<=not model1;
  clocknum: count64 Port map
         ( sysclk => sysclk,
           reset => reset,
           clkout => clk
			  );
 
  mousedata: mouse Port map
       (  clk => clk,
          reset => reset,
          ps2_clk => ps2clk,
          ps2_data => ps2data,
          left_button => left_button,
          right_button => right_button,
		    mousex => mousex,
		    mousey => mousey,
          data_ready => read,
          --read : in std_logic; -- rx_read_ack_i
          error_no_ack => error_no_ack
			 );


  showdata: vgacore port map
	(
		reset => reset,
		clock => sysclk,
		hsyncb => hsyncb,
		vsyncb => vsyncb,
      model => model,
		rgb => rgb,
		read_data => read,
		lbutton => left_button,
		rbutton => right_button,
		mousex => mousex,
		mousey => mousey
);

end Behavioral;