top.par

这是非常好的vhdl例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

EESTD::  Thu Dec 02 09:30:13 2004


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolved that IOB <ps2data> must be placed at site P5.
Resolved that IOB <sysclk> must be placed at site P80.
Resolved that IOB <vsyncb> must be placed at site P35.
Resolved that IOB <rgb<0>> must be placed at site P33.
Resolved that IOB <rgb<1>> must be placed at site P34.
Resolved that IOB <rgb<2>> must be placed at site P29.
Resolved that IOB <ps2clk> must be placed at site P7.
Resolved that IOB <model1<0>> must be placed at site P37.
Resolved that IOB <model1<1>> must be placed at site P39.
Resolved that IOB <model1<2>> must be placed at site P40.
Resolved that IOB <reset1> must be placed at site P45.
Resolved that IOB <hsyncb> must be placed at site P36.


Device utilization summary:

   Number of External IOBs            12 out of 141     8%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of Slices                  215 out of 3584    5%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989a0d) REAL time: 2 secs 

.
Phase 3.8
................
Phase 3.8 (Checksum:9aee25) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1187 unrouted;       REAL time: 4 secs 

Phase 2: 1068 unrouted;       REAL time: 5 secs 

Phase 3: 336 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|      sysclk_BUFGP       |  BUFGMUX1| No   |   33 |  0.047     |  0.630      |
+-------------------------+----------+------+------+------------+-------------+
| clocknum_count<6>       |   Local  |      |   58 |  0.353     |  2.715      |
+-------------------------+----------+------+------+------------+-------------+
|   showdata_hsyncb       |   Local  |      |    8 |  1.583     |  3.987      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 168


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.120
   The MAXIMUM PIN DELAY IS:                               3.987
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.795

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         646         358         146          37           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.