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这是非常好的vhdl例子

#      IOBUF                       : 2
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     211  out of   3584     5%  
 Number of Slice Flip Flops:           159  out of   7168     2%  
 Number of 4 input LUTs:               345  out of   7168     4%  
 Number of bonded IOBs:                 11  out of    141     7%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sysclk                             | BUFGP                  | 53    |
clocknum_count_6:Q                 | NONE                   | 95    |
showdata_hsyncb:Q                  | NONE                   | 11    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.450ns (Maximum Frequency: 408.163MHz)
   Minimum input arrival time before clock: 2.856ns
   Maximum output required time after clock: 6.753ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sysclk'
Delay:               1.919ns (Levels of Logic = 4)
  Source:            showdata_hcnt_10 (FF)
  Destination:       showdata_rgb_0 (FF)
  Source Clock:      sysclk rising
  Destination Clock: sysclk rising

  Data Path: showdata_hcnt_10 to showdata_rgb_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             19   0.000   1.102  showdata_hcnt_10 (showdata_hcnt_10)
     LUT1:I0->O            1   0.000   0.000  showdata_Mcompar__n0078_inst_lut2_8511 (showdata_Mcompar__n0078_inst_lut2_85)
     MUXCY:S->O            1   0.000   0.240  showdata_Mcompar__n0078_inst_cy_84 (showdata_Mcompar__n0078_inst_cy_84)
     LUT4:I0->O            3   0.000   0.577  showdata__n00374 (CHOICE54)
     LUT4:I0->O            1   0.000   0.000  showdata_Mmux__n0026_Result<0>1 (showdata__n0026<0>)
     FD:D                      0.000          showdata_rgb_0
    ----------------------------------------
    Total                      1.919ns (0.000ns logic, 1.919ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clocknum_count_6:Q'
Delay:               2.450ns (Levels of Logic = 6)
  Source:            mousedata_q_6 (FF)
  Destination:       mousedata_mousey_7 (FF)
  Source Clock:      clocknum_count_6:Q rising
  Destination Clock: clocknum_count_6:Q rising

  Data Path: mousedata_q_6 to mousedata_mousey_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.000   0.658  mousedata_q_6 (mousedata_q_6)
     LUT4:I0->O            1   0.000   0.240  mousedata__n012651 (CHOICE199)
     LUT4_L:I3->LO         1   0.000   0.100  mousedata__n012669 (CHOICE202)
     LUT4:I3->O            2   0.000   0.465  mousedata__n0126102 (CHOICE205)
     LUT4:I3->O            1   0.000   0.000  mousedata__n0126165_F (N16355)
     MUXF5:I0->O           1   0.000   0.240  mousedata__n0126165 (CHOICE209)
     LUT2_D:I1->O          8   0.000   0.747  mousedata__n0126178 (mousedata__n0126)
     FDCE:CE                   0.000          mousedata_mousey_1
    ----------------------------------------
    Total                      2.450ns (0.000ns logic, 2.450ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'showdata_hsyncb:Q'
Delay:               1.882ns (Levels of Logic = 3)
  Source:            showdata_vcnt_3 (FF)
  Destination:       showdata_vcnt_8 (FF)
  Source Clock:      showdata_hsyncb:Q rising
  Destination Clock: showdata_hsyncb:Q rising

  Data Path: showdata_vcnt_3 to showdata_vcnt_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             11   0.000   0.836  showdata_vcnt_3 (showdata_vcnt_3)
     LUT4:I0->O            1   0.000   0.240  showdata_Mcompar__n0032_Ker341617 (CHOICE67)
     LUT4:I2->O           10   0.000   0.806  showdata_Mcompar__n0032_Ker341642 (CHOICE71)
     LUT4:I1->O            1   0.000   0.000  showdata__n0019<8>1 (showdata__n0019<8>)
     FDC:D                     0.000          showdata_vcnt_8
    ----------------------------------------
    Total                      1.882ns (0.000ns logic, 1.882ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clocknum_count_6:Q'
Offset:              2.856ns (Levels of Logic = 2)
  Source:            reset1 (PAD)
  Destination:       mousedata_mouseyy_8 (FF)
  Destination Clock: clocknum_count_6:Q rising

  Data Path: reset1 to mousedata_mouseyy_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           132   0.641   1.409  reset1_IBUF (reset1_IBUF)
     LUT2:I1->O           10   0.000   0.806  mousedata__n00211 (mousedata__n0021)
     FDE:CE                    0.000          mousedata_mouseyy_0
    ----------------------------------------
    Total                      2.856ns (0.641ns logic, 2.215ns route)
                                       (22.4% logic, 77.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk'
Offset:              2.050ns (Levels of Logic = 1)
  Source:            reset1 (PAD)
  Destination:       showdata_mousevcnt_9 (FF)
  Destination Clock: sysclk rising

  Data Path: reset1 to showdata_mousevcnt_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           132   0.641   1.409  reset1_IBUF (reset1_IBUF)
     FDR:R                     0.000          showdata_mousehcnt_9
    ----------------------------------------
    Total                      2.050ns (0.641ns logic, 1.409ns route)
                                       (31.3% logic, 68.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clocknum_count_6:Q'
Offset:              6.753ns (Levels of Logic = 2)
  Source:            mousedata_m2_state_FFd4 (FF)
  Destination:       ps2data (PAD)
  Source Clock:      clocknum_count_6:Q rising

  Data Path: mousedata_m2_state_FFd4 to ps2data
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.000   0.577  mousedata_m2_state_FFd4 (mousedata_m2_state_FFd4)
     LUT3:I0->O            1   0.000   0.240  mousedata_m2_state_Out21 (mousedata_ps2_data_hi_z)
     IOBUF:T->IO               5.936          ps2data_IOBUF (ps2data)
    ----------------------------------------
    Total                      6.753ns (5.936ns logic, 0.817ns route)
                                       (87.9% logic, 12.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'showdata_hsyncb:Q'
Offset:              5.820ns (Levels of Logic = 1)
  Source:            showdata_vsyncb (FF)
  Destination:       vsyncb (PAD)
  Source Clock:      showdata_hsyncb:Q rising

  Data Path: showdata_vsyncb to vsyncb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              1   0.000   0.240  showdata_vsyncb (showdata_vsyncb)
     OBUF:I->O                 5.580          vsyncb_OBUF (vsyncb)
    ----------------------------------------
    Total                      5.820ns (5.580ns logic, 0.240ns route)
                                       (95.9% logic, 4.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk'
Offset:              6.445ns (Levels of Logic = 1)
  Source:            showdata_hsyncb (FF)
  Destination:       hsyncb (PAD)
  Source Clock:      sysclk rising

  Data Path: showdata_hsyncb to hsyncb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q             12   0.000   0.865  showdata_hsyncb (showdata_hsyncb)
     OBUF:I->O                 5.580          hsyncb_OBUF (hsyncb)
    ----------------------------------------
    Total                      6.445ns (5.580ns logic, 0.865ns route)
                                       (86.6% logic, 13.4% route)

=========================================================================
CPU : 22.41 / 24.66 s | Elapsed : 22.00 / 25.00 s
 
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Total memory usage is 75956 kilobytes