top.syr

这是非常好的vhdl例子

    Register <risesig<0>> equivalent to <fallsig<0>> has been removed
    Found finite state machine <FSM_0> for signal <m2_state>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 29                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | m2_reset                                       |
    | Power Up State     | m2_reset                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <q<6>> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <q<19>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 1-bit tristate buffer for signal <ps2_clk>.
    Found 1-bit tristate buffer for signal <ps2_data>.
    Found 1-bit register for signal <right_button>.
    Found 1-bit register for signal <left_button>.
    Found 10-bit up accumulator for signal <mousex>.
    Found 10-bit up accumulator for signal <mousey>.
    Found 10-bit adder for signal <$n0029> created at line 299.
    Found 11-bit comparator greatequal for signal <$n0037> created at line 311.
    Found 11-bit comparator lessequal for signal <$n0038> created at line 311.
    Found 11-bit comparator greatequal for signal <$n0039> created at line 326.
    Found 11-bit comparator lessequal for signal <$n0040> created at line 326.
    Found 6-bit up counter for signal <bitcount>.
    Found 3-bit register for signal <fallsig>.
    Found 10-bit register for signal <mouseyy>.
    Found 33-bit register for signal <q>.
    Found 2-bit register for signal <risesig<2:1>>.
    Found 9-bit up counter for signal <watchdog_timer_count>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred   2 Accumulator(s).
	inferred  50 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred   2 Tristate(s).
Unit <mouse> synthesized.


Synthesizing Unit <count64>.
    Related source file is E:/work/digital_sward/sub_DEMO/submouse/Count64.vhd.
    Found 7-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <count64> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/work/digital_sward/sub_DEMO/submouse/Top.vhd.
WARNING:Xst:646 - Signal <error_no_ack> is assigned but never used.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <m2_state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 11
 10-bit adder                      : 2
 11-bit adder                      : 1
 9-bit adder                       : 2
 8-bit adder                       : 2
 10-bit subtractor                 : 4
# Counters                         : 3
 6-bit up counter                  : 1
 7-bit up counter                  : 1
 9-bit up counter                  : 1
# Accumulators                     : 2
 10-bit up accumulator             : 2
# Registers                        : 66
 10-bit register                   : 4
 1-bit register                    : 56
 3-bit register                    : 5
 11-bit register                   : 1
# Comparators                      : 26
 11-bit comparator greatequal      : 6
 11-bit comparator lessequal       : 7
 10-bit comparator lessequal       : 2
 10-bit comparator greatequal      : 2
 12-bit comparator lessequal       : 3
 12-bit comparator greatequal      : 2
 11-bit comparator greater         : 1
 12-bit comparator greater         : 1
 11-bit comparator less            : 1
 12-bit comparator less            : 1
# Multiplexers                     : 2
 3-bit 8-to-1 multiplexer          : 1
 3-bit 2-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2
# Xors                             : 5
 3-bit xor2                        : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <frame_0> (without init value) is constant in block <vgacore>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <frame_1> (without init value) is constant in block <vgacore>.
WARNING:Xst:1291 - FF/Latch <FFd2> is unconnected in block <m2_state>.
WARNING:Xst:1291 - FF/Latch <mousedata_m2_state_FFd2> is unconnected in block <top>.

Optimizing unit <top> ...

Optimizing unit <vgacore> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register mousedata_risesig_1 equivalent to mousedata_fallsig_1 has been removed
Register mousedata_risesig_2 equivalent to mousedata_fallsig_2 has been removed
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 6.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 92
#      1-bit register              : 82
#      10-bit register             : 2
#      11-bit register             : 1
#      3-bit register              : 5
#      7-bit register              : 2
# Counters                         : 1
#      6-bit up counter            : 1
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 1
#      3-bit 8-to-1 multiplexer    : 1
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 15
#      10-bit adder                : 4
#      10-bit subtractor           : 4
#      11-bit adder                : 1
#      7-bit adder                 : 2
#      8-bit adder                 : 2
#      9-bit adder                 : 2
# Comparators                      : 26
#      10-bit comparator greatequal: 2
#      10-bit comparator lessequal : 2
#      11-bit comparator greatequal: 6
#      11-bit comparator greater   : 1
#      11-bit comparator less      : 1
#      11-bit comparator lessequal : 7
#      12-bit comparator greatequal: 2
#      12-bit comparator greater   : 1
#      12-bit comparator less      : 1
#      12-bit comparator lessequal : 3

Cell Usage :
# BELS                             : 705
#      GND                         : 1
#      LUT1                        : 128
#      LUT2                        : 105
#      LUT2_D                      : 1
#      LUT2_L                      : 1
#      LUT3                        : 16
#      LUT3_D                      : 3
#      LUT3_L                      : 11
#      LUT4                        : 64
#      LUT4_D                      : 2
#      LUT4_L                      : 14
#      MUXCY                       : 216
#      MUXF5                       : 5
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 136
# FlipFlops/Latches                : 159
#      FD                          : 3
#      FDC                         : 47
#      FDCE                        : 56
#      FDCPE                       : 6
#      FDE                         : 11
#      FDP                         : 3
#      FDPE                        : 7
#      FDR                         : 19
#      FDS                         : 7
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 4