top.syr

这是非常好的vhdl例子

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.34 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.35 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was e:/work/coreban/submouse/Top.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was e:/work/coreban/submouse/Top.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Top.vhd
WARNING:HDLParsers:3215 - Unit work/VGACORE is now defined in a different file: was e:/work/coreban/submouse/Vgacore.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd
WARNING:HDLParsers:3215 - Unit work/VGACORE/VGACORE_ARCH is now defined in a different file: was e:/work/coreban/submouse/Vgacore.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE is now defined in a different file: was e:/work/coreban/submouse/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE/BEHAVIORAL is now defined in a different file: was e:/work/coreban/submouse/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64 is now defined in a different file: was e:/work/coreban/submouse/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Count64.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64/BEHAVIORAL is now defined in a different file: was e:/work/coreban/submouse/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/submouse/Count64.vhd
Compiling vhdl file E:/work/digital_sward/sub_DEMO/submouse/Count64.vhd in Library work.
Architecture behavioral of Entity count64 is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/submouse/Mouse.vhd in Library work.
Architecture behavioral of Entity mouse is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd in Library work.
Architecture vgacore_arch of Entity vgacore is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/submouse/Top.vhd in Library work.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 12: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/submouse/Top.vhd line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <count64> (Architecture <behavioral>).
Entity <count64> analyzed. Unit <count64> generated.

Analyzing Entity <mouse> (Architecture <behavioral>).
Entity <mouse> analyzed. Unit <mouse> generated.

Analyzing Entity <vgacore> (Architecture <vgacore_arch>).
INFO:Xst:1561 - E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd line 132: Mux is complete : default of case is discarded
INFO:Xst:1561 - E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd line 143: Mux is complete : default of case is discarded
INFO:Xst:1561 - E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd line 182: Mux is complete : default of case is discarded
Entity <vgacore> analyzed. Unit <vgacore> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgacore>.
    Related source file is E:/work/digital_sward/sub_DEMO/submouse/Vgacore.vhd.
WARNING:Xst:647 - Input <read_data> is never used.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <hsyncb>.
    Found 3-bit register for signal <rgb>.
    Found 10-bit subtractor for signal <$n0010> created at line 170.
    Found 10-bit subtractor for signal <$n0012> created at line 170.
    Found 8-bit adder for signal <$n0027> created at line 170.
    Found 9-bit adder for signal <$n0028> created at line 170.
    Found 9-bit adder for signal <$n0029> created at line 170.
    Found 8-bit adder for signal <$n0030> created at line 170.
    Found 12-bit comparator less for signal <$n0031> created at line 48.
    Found 11-bit comparator less for signal <$n0032> created at line 64.
    Found 3-bit 8-to-1 multiplexer for signal <$n0039>.
    Found 3-bit xor2 for signal <$n0040> created at line 182.
    Found 3-bit xor2 for signal <$n0041> created at line 181.
    Found 3-bit xor2 for signal <$n0042> created at line 180.
    Found 3-bit xor2 for signal <$n0043> created at line 179.
    Found 3-bit xor2 for signal <$n0044> created at line 178.
    Found 11-bit adder for signal <$n0048> created at line 49.
    Found 10-bit adder for signal <$n0049> created at line 65.
    Found 12-bit comparator greatequal for signal <$n0066> created at line 80.
    Found 12-bit comparator lessequal for signal <$n0067> created at line 80.
    Found 11-bit comparator greatequal for signal <$n0068> created at line 96.
    Found 11-bit comparator lessequal for signal <$n0069> created at line 96.
    Found 12-bit comparator greater for signal <$n0070> created at line 112.
    Found 11-bit comparator greater for signal <$n0071> created at line 112.
    Found 12-bit comparator lessequal for signal <$n0072> created at line 157.
    Found 12-bit comparator greatequal for signal <$n0073> created at line 157.
    Found 12-bit comparator lessequal for signal <$n0074> created at line 157.
    Found 11-bit comparator lessequal for signal <$n0075> created at line 157.
    Found 11-bit comparator greatequal for signal <$n0076> created at line 157.
    Found 11-bit comparator lessequal for signal <$n0077> created at line 157.
    Found 11-bit comparator greatequal for signal <$n0078> created at line 170.
    Found 11-bit comparator lessequal for signal <$n0079> created at line 170.
    Found 10-bit subtractor for signal <$n0080> created at line 170.
    Found 10-bit comparator greatequal for signal <$n0081> created at line 170.
    Found 10-bit comparator lessequal for signal <$n0082> created at line 170.
    Found 10-bit subtractor for signal <$n0083> created at line 170.
    Found 10-bit comparator greatequal for signal <$n0084> created at line 170.
    Found 10-bit comparator lessequal for signal <$n0085> created at line 170.
    Found 11-bit comparator greatequal for signal <$n0086> created at line 170.
    Found 11-bit comparator lessequal for signal <$n0087> created at line 170.
    Found 3-bit register for signal <bangcolor>.
    Found 3-bit register for signal <frame>.
    Found 11-bit register for signal <hcnt>.
    Found 3-bit register for signal <hrgb>.
    Found 10-bit register for signal <mousehcnt>.
    Found 10-bit register for signal <mousevcnt>.
    Found 1-bit register for signal <pblank>.
    Found 10-bit register for signal <vcnt>.
    Found 3-bit register for signal <vrgb>.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred  10 Adder/Subtracter(s).
	inferred  22 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <vgacore> synthesized.


Synthesizing Unit <mouse>.
    Related source file is E:/work/digital_sward/sub_DEMO/submouse/Mouse.vhd.
WARNING:Xst:646 - Signal <packet_good> is assigned but never used.
WARNING:Xst:646 - Signal <q<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <clean_clk> is never used or assigned.
WARNING:Xst:1780 - Signal <n_rise> is never used or assigned.
WARNING:Xst:1780 - Signal <n_fall> is never used or assigned.