555_etas_init.c

摩托罗拉处理器mpc855上的UCOS移植代码

/****************************************************************************/
/*

FILE
	
	555_ETAS_init.c
	
DESCRIPTION

	This is the board initialization file for the Motorola 555 ETAS
	eval board.  It is derived from the BDM initialization file described
	in section 7.2 in the document "Using the MIOS on the MPC555 Evaluation
	Board" (Motorola document AN1778/D).
		
HISTORY
	
	$History: 555_ETAS_init.c $
	
	Nov 04, 1999:
	Sutanto		Adapted from MetroTRK's init_555_etas.c file.
	

AUTHORS

	Steve Moore

	(c) 1999 Metrowerks Corporation
	All rights reserved.
	
*/
/****************************************************************************/

#pragma section code_type ".init"

#define SIUMCR				0x2fc000
#define SYPCR				0x2fc004
#define SIPEND				0x2fc010
#define SIMASK				0x2fc014
#define SIEL				0x2fc018
#define SIVEC				0x2fc01c
#define BR0					0x2fc100
#define OR0					0x2fc104
#define BR1					0x2fc108
#define OR1					0x2fc10c
#define BR2					0x2fc110
#define OR2					0x2fc114
#define BR3					0x2fc118
#define OR3					0x2fc11c
#define DMBR				0x2fc140
#define DMOR				0x2fc144
#define PLPRCR				0x2fc284

#define DPTMCR				0x300000
#define RAMBAR				0x300004
#define PORTQS				0x305014
#define PQSPAR				0x305016
#define MPIOSMDR			0x306100
#define MPIOSMDDR			0x306102
#define MIOS1TPCR			0x306800
#define SRAMMCR				0x380000
#define SGPIODT1			0x2fc024
#define SGPIODT2			0x2fc028
#define SGPIOCR				0x2fc02c
#define EMCR				0x2fc030
#define UMCR				0x307f80

//SPR defines
#define SPR_SRR1			27
#define SPR_IMMR			638
#define SPR_BBCMCR			560			

#ifdef __cplusplus
extern "C" {
#endif

asm void __reset(void);
asm void usr_init();
extern void __start();

#ifdef __cplusplus
}
#endif

asm void __reset(void)
{
	//
	//   Enable machine check exceptions
	//
		lis		r3, 0
		ori		r3, r3, 0x1002
		mtmsr	r3
		
	//
	//	ROM is not relocated, so nothing left to do here.
	//

		b		__start
}

asm void usr_init()
{
		nofralloc
		
		/*
		** Make the processor to run at 40MHz ( (9+1) * 4 MHz)
		** by programming PLPRCR register with
		** value 0x00904000.		
		**
		*/
		lis			r4, PLPRCR@ha
		lwz			r5, PLPRCR@l(r4)
		lis			r5, 0x0090
		ori			r5, r5, 0x4000
		stw			r5, PLPRCR@l(r4)

		li			r0, 0			/* put 0 in r0 for convenience */

		/*
		** MSR	(Machine Check Enable and Can recover from Reset and Machine Check)
		*/

		ori			r5, r0, 0x3002
		mtmsr		r5				/* RI=1, IP=0, ME=1, FP=1 */
		mtspr		SPR_SRR1, r5	/* SRR1 */

		/*
		** Set IMMR:
		**	FLEN[20] = 1 (enable on-chip flash)
		**	CLES[23] = 0 (little-endian swap logic not activated)
		**	ISB[28:30] = 000 (internal mem at 0x00000000)
		*/
		
		ori			r5, r0, 0x0800
		mtspr		SPR_IMMR, r5
		
		// BBCMCR=0x0
		mtspr		SPR_BBCMCR, r0
		
		// SIUMCR=0x0
		lis			r4, SIUMCR@ha
		stw			r0, SIUMCR@l(r4)

		// SYPCR=0xFF88
		ori			r5, r0, 0xff88
		lis			r4, SYPCR@ha
		stw			r5, SYPCR@l(r4)

		// BR0=0x00800003
		lis			r5, 0x0080
		ori			r5, r5, 0x0003
		lis			r4, BR0@ha
		stw			r5, BR0@l(r4)

		// OR0=0xFFF80012
		lis			r5, 0xfff8
		ori			r5, r5, 0x0012
		lis			r4, OR0@ha
		stw			r5, OR0@l(r4)

		// BR1=0x00C00003
		lis			r5, 0x00c0
		ori			r5, r5, 0x0003
		lis			r4, BR1@ha
		stw			r5, BR1@l(r4)

		// OR1=0xFFC00000
		lis			r5, 0xffc0
		lis			r4, OR1@ha
		stw			r5, OR1@l(r4)

		// BR2=0x06000003
		lis			r5, 0x0600
		ori			r5, r5, 0x0003
		lis			r4, BR2@ha
		stw			r5, BR2@l(r4)

		// OR2=0xFFFF8000
		lis			r5, 0xffff
		ori			r5, r5, 0x8000
		lis			r4, OR2@ha
		stw			r5, OR2@l(r4)

		// BR3=0x00000000
		lis			r4, BR3@ha
		stw			r0, BR3@l(r4)

		// OR3=0x00000000
		lis			r4, OR3@ha
		stw			r0, OR3@l(r4)

		// DMBR=0x00000003
//		li			r5, 0x0003
//		lis			r4, DMBR@ha
//		stw			r5, DMBR@l(r4)

		// DMOR=0x7E080000
//		lis			r5, 0x7e08
//		lis			r4, DMOR@ha
//		stw			r5, DMOR@l(r4)

		// DPTMCR=0x0000
		lis			r4, DPTMCR@ha
		sth			r0, DPTMCR@l(r4)

		// RAMBAR=0xFFA0
		li			r5, 0xffa0
		lis			r4, RAMBAR@ha
		sth			r5, RAMBAR	@l(r4)

		// PORTQS=0x0000
		lis			r4, PORTQS@ha
		sth			r0, PORTQS@l(r4)

		// PQSPAR/DDRQS=0x0000
		lis			r4, PQSPAR@ha
		sth			r0, PQSPAR@l(r4)

		// MPIOSMDR=0x0000
		lis			r4, MPIOSMDR@ha
		sth			r0, MPIOSMDR@l(r4)

		// MPIOSMDDR=0x0000
		lis			r4, MPIOSMDDR@ha
		sth			r0, MPIOSMDDR@l(r4)

		// MIOS1TPCR=0x0000
		lis			r4, MIOS1TPCR@ha
		sth			r5, MIOS1TPCR@l(r4)

		// SRAMMCR=0x00000000
		lis			r4, SRAMMCR@ha
		stw			r0, SRAMMCR@l(r4)

		// SGPIODT1=0x00000000
		lis			r4, SGPIODT1@ha
		stw			r0, SGPIODT1@l(r4)

		// SGPIODT2=0x00000000
		lis			r4, SGPIODT2@ha
		stw			r0, SGPIODT2@l(r4)

		// SGPIOCR=0x00000000
		lis			r4, SGPIOCR@ha
		stw			r0, SGPIOCR@l(r4)

		// EMCR=0x00000000
		lis			r4, EMCR@ha
		stw			r0, EMCR@l(r4)

		// UMCR=0x00000000
		lis			r4, UMCR@ha
		stw			r0, UMCR@l(r4)
		
		blr
}