📄 os_cpu_a.s
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; ;
; ;
; u C / O S - II EP7209 P O R T ;
; ;
; FILE : os_cpu_a.s ;
; ;
; Ported By zartoven@zuguri.org January 29, 2001 ;
; ;
; This port is tested on NANOWIT EP7209 Board ;
; ;
; To get information about NANOWIT, Visit www.nanowit.com ;
; ;
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;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; Stack Area Definition ;
;.......................................................................;
RAMLimit EQU 0x00109600 ; Internal Sram end
SVCStackSize EQU 0x1000
IRQStackSize EQU 0x100
FIQStackSize EQU 0x100
SVCStackEnd EQU RAMLimit
IRQStackEnd EQU SVCStackEnd-SVCStackSize
FIQStackEnd EQU IRQStackEnd-IRQStackSize
;.......................................................................;
; EP7209 Internal Register Definition ;
;.......................................................................;
REGISTER_BASE EQU 0x00200000
HwControl EQU 0x00000100
HwControlUartEnable EQU 0x00000100
HwStatus2 EQU 0x00001140
CLKMOD EQU 0x40
UartValue EQU 0x00060001
UartValue_13 EQU 0x00060000
HwUartData EQU 0x00000480
HwUartData2 EQU 0x00001480
HwUartControl EQU 0x000004c0
HwUartControl2 EQU 0x000014c0
CLKCTL_73 EQU 0x6
SYSCON1 EQU 0x00000100
TC1D EQU 0x00000300
INTSR1 EQU 0x00000240
INTMR1 EQU 0x00000280
TC1EOI EQU 0x000006c0
;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; Program Start!!! ;
;.......................................................................;
AREA |Assembly$$code|, CODE, READONLY
ENTRY
;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; Vector Table ;
;.......................................................................;
b ResetHandler
ldr pc, UndefV
ldr pc, SWIV
ldr pc, PAbortV
ldr pc, DAbortV
ldr pc, UnusedV
ldr pc, IRQV
ldr pc, FIQV
UndefV
DCD UndefHandler
SWIV
DCD SWIHandler
PAbortV
DCD PAbortHandler
DAbortV
DCD DAbortHandler
UnusedV
DCD UnusedHandler
IRQV
DCD IRQHandler
FIQV
DCD FIQHandler
UndefHandler
movs pc, lr
SWIHandler
movs pc, lr
PAbortHandler
subs pc, lr, #4
DAbortHandler
subs pc, lr, #8
UnusedHandler
movs pc, lr
FIQHandler
subs pc, lr, #4
;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; IRQHandler is very important ;
;.......................................................................;
IRQHandler
stmfd sp!,{r0-r3}
mov r1,#REGISTER_BASE
ldr r2,=INTSR1
ldr r0,[r1,r2]
tst r0,#0x100
bne TimerIRQ ; Check Timer IRQ
;
; if use other IRQ, follow Timer IRQ type...
;
ldmfd sp!,{r0-r3}
subs pc,lr,#4
;------------------------------------------------------------------------
; Timer IRQ Header Part..
;
TimerIRQ
ldr r2,=TC1EOI ; Timer 1 Interrupt Clear
str r0,[r1,r2]
mov r2,sp ; copy IRQ's sp -> r2
add sp,sp,#16 ; recover IRQ's sp
sub r3,lr,#4 ; copy return address -> r3
LDR r0,=IRQ_2
MOVS pc,r0
IRQ_2
stmfd sp!,{r3} ; push SVC's pc
stmfd sp!,{r4-r12,lr} ; push SVC's r14, r12-r4
mov r4,r2
ldmfd r4!,{r0-r3}
stmfd sp!,{r0-r3} ; push SVC's r3-r0
mrs r5,cpsr
stmfd sp!,{r5} ; push SVC's PSR
;
; This IRQ Header is needed for other IRQ Handler
;------------------------------------------------------------------------
B OSTickISR ; Real Body...
;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; Starting Point!!!! ;
;.......................................................................;
ResetHandler
ldr r0, =0x80002200 ; Clock Speed Setting
ldr r1, [r0]
orr r1, r1, #CLKCTL_73
strb r1, [r0]
;------------------------------------------------------------------------
; Stack Point Setting Each CPU Mode
;
ldr r0, =0x000000d2 ; IRQ Mode sp Setting
msr cpsr_cf, r0
ldr r13, =IRQStackEnd
ldr r0, =0x000000d1 ; FIQ Mode sp Setting
msr cpsr_cf, r0
ldr r13, =FIQStackEnd
ldr r0, =0x000000d3 ; SVC Mode sp Setting
msr cpsr_cf, r0
ldr r13, =SVCStackEnd
;------------------------------------------------------------------------
; MMU Configuration
;
ldr r0, =0x00000000
mcr p15, 0, r0, c5, c0
mcr p15, 0, r0, c7, c0
ldr r0, =0x55555555
mcr p15, 0, r0, c3, c0
IMPORT PageTable
ldr r0, =PageTable
mcr p15, 0, r0, c2, c0
ldr r0, =0x0000007d
mcr p15, 0, r0, c1, c0
;
; There should always be two NOP instructions following the enable or
; disable of the MMU.
;
mov r0, r0
mov r0, r0
;
; Delay for MMU
;
ldr r1, =0x0
ldr r2, =0x100
delay
cmp r1, r2
ldrne r3, [r1], #4
bne delay
;------------------------------------------------------------------------
; Variable Area Initialization
;
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq %1
0 cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc %0
1 ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
2 cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %2
;------------------------------------------------------------------------
; Serial Port Initialization
; 115200 BPS, Data bit 8 Bit, No Parity, Stop Bit 1 Bit
;
ldr r12, =REGISTER_BASE
mov r0, #HwControlUartEnable
str r0, [r12, #HwControl]
ldr r1, =HwStatus2
add r1,r1,r12
ldr r2, [r1]
tst r2, #CLKMOD
ldreq r0, =UartValue
ldrne r0, =UartValue_13
str r0, [r12, #HwUartControl]
;------------------------------------------------------------------------
; Timer1 Setting = 10ms period
;
mov r1,#REGISTER_BASE
ldr r2,=SYSCON1
ldr r0,[r1,r2]
bic r0,r0,#0x20
orr r0,r0,#0x10
str r0,[r1,r2]
ldr r2,=TC1D
ldr r0,=21 ; 2115 -> 1 Second, 21 -> 10ms
str r0,[r1,r2]
ldr r2,=INTMR1
ldr r0,[r1,r2]
orr r0,r0,#0x100
str r0,[r1,r2]
ldr r2,=TC1EOI
mov r0,#0
str r0,[r1,r2]
;------------------------------------------------------------------------
; C Routine Entry Point
;
IMPORT C_Entry
b C_Entry
;''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''';
; Simple Subrutine ;
;.......................................................................;
;------------------------------------------------------------------------
; void SendChar(char ch) // Put a character to UART
;
EXPORT SendChar
SendChar
mov r1, #REGISTER_BASE
WLoop
ldr r2, [r1, #0x0140]
tst r2, #0x00800000
bne WLoop
str r0, [r1, #0x0480]
mov pc, lr
;------------------------------------------------------------------------
; int splx(int onoff) // IRQ On/Off
; // onoff : 1 -> IRQ Disable
; // onoff : 0 -> IRQ Enable
EXPORT splx
splx
MRS r1, cpsr
BIC r2, r1, #0x80
CMP r0, #1
ORREQ r2, r2, #0x80
MSR CPSR_cxsf, r2
MOVS r1, r1, LSL #25
MOV r0, #0
MOVCS r0, #1
mov pc,lr
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------;
; uC/OS Porting Core Function : OSStartHighRdy ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
IMPORT OSTaskSwHook
IMPORT OSRunning
IMPORT OSTCBHighRdy
EXPORT OSStartHighRdy
OSStartHighRdy
BL OSTaskSwHook ; Call user defined task switch hook
LDR r0,=OSRunning ; Indicate that multitasking has started
MOV r1,#1
STRB r1,[r0]
LDR r0,=OSTCBHighRdy ; r0 <= &OSTCBHighRdy
LDR r0,[r0] ; r0 <= OSTCBHighRdy
LDR sp,[r0] ; sp <= OSTCBHighRdy->OSTCBStkPtr
LDMFD sp!,{r0} ; restore SP...
MSR CPSR_xsf,r0
LDMFD sp!,{r0 - r12, lr , pc} ; Load task's context & Run task
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------;
; uC/OS Porting Core Function : OSCtxSw ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
IMPORT OSTCBCur
IMPORT OSTaskSwHook
IMPORT OSTCBHighRdy
IMPORT OSPrioCur
IMPORT OSPrioHighRdy
EXPORT OSCtxSw
OSCtxSw
STMFD sp!,{lr} ; push resume address
STMFD sp!,{r0 - r12, lr} ; push rest context
MRS r0,CPSR
STMFD sp!,{r0} ; push CPSR
LDR r0,=OSTCBCur ; r0 <= &OSTCBCur
LDR r0,[r0] ; r0 <= OSTCBCur
STR sp,[r0] ; OSTCBCur->OSTCBStkPtr = sp
BL OSTaskSwHook ; Call user defined task switch hook
LDR r0,=OSTCBCur ; r0 <= &OSTCBCur
LDR r1,=OSTCBHighRdy ; r1 <= &OSTCBHighRdy
LDR r2,[r1] ; r2 <= OSTCBHighRdy
STR r2,[r0] ; OSTCBCur = OSTCBHighRdy
LDR r0,=OSPrioCur ; r0 <= &OSPrioCur
LDR r1,=OSPrioHighRdy ; r1 <= &OSPrioHighRdy
LDRB r3,[r1] ; r3 <= OSPrioHighRdy
STRB r3,[r0] ; OSPrioCur = OSPrioHighRdy
LDR sp,[r2] ; sp <= OSTCBHighRdy->OSTCBStkPtr
LDMFD sp!,{r0} ; restore SP...
MSR CPSR_xsf,r0
LDMFD sp!,{r0 - r12, lr , pc} ; Load task's context & Run task
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------;
; uC/OS Porting Core Function : OSIntCtxSw ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
IMPORT OSTCBCur
IMPORT OSTaskSwHook
IMPORT OSTCBHighRdy
IMPORT OSPrioCur
IMPORT OSPrioHighRdy
EXPORT OSIntCtxSw
OSIntCtxSw
ADD sp,sp,#4
LDR r0,=OSTCBCur ; r0 <= &OSCTBCur
LDR r0,[r0] ; r0 <= OSCTBCur
STR sp,[r0] ; OSTCBCur->OSTCBStkPtr = sp
BL OSTaskSwHook ; Call user defined task switch hook
LDR r0,=OSTCBCur ; r0 <= &OSTCBCur
LDR r1,=OSTCBHighRdy ; r1 <= &OSTCBHighRdy
LDR r2,[r1] ; r2 <= OSTCBHighRdy
STR r2,[r0] ; OSTCBCur = OSTCBHighRdy
LDR r0,=OSPrioCur ; r0 <= &OSPrioCur
LDR r1,=OSPrioHighRdy ; r1 <= &OSPrioHighRdy
LDRB r3,[r1] ; r3 <= OSPrioHighRdy
STRB r3,[r0] ; OSPrioCur = OSPrioHighRdy
LDR sp,[r2] ; sp <= OSTCBHighRdy->OSTCBStkPtr
LDMFD sp!,{r0} ; restore SP...
MSR CPSR_xsf,r0
LDMFD sp!,{r0 - r12, lr , pc} ; Load task's context & Run task
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------;
; uC/OS Porting Core Function : OSTickISR ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
IMPORT OSIntNesting
IMPORT OSTimeTick
IMPORT OSIntExit
OSTickISR
LDR r0,=OSIntNesting ; Notify uC/OS-II of ISR
LDRB r1,[r0]
ADD r1,r1,#1
STRB r1,[r0]
BL OSTimeTick ; Process system tick
BL OSIntExit ; Notify uC/OS-II of end of ISR
LDMFD sp!,{r0}
MSR CPSR_xsf,r0
LDMFD sp!,{r0 - r12, lr , pc}
END
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