cstartup_boot_sam7s64.s

ATMEL公司的demo程序,USB驱动程序,与识别片上flash,并进行枚举和操作.

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source          : cstartup_boot.arm
;- Object               : Generic CStartup
;- Compilation flag     : None
;-
;- 1.0 01/22/04 	FBr : Creation ARM ADS
;------------------------------------------------------------------------------

;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
;------------------------------------------------------------------------------
                AREA        reset, CODE, READONLY

	INCLUDE		AT91SAM7S64.inc

;------------------------------------------------------------------------------
;- Define the entry point
;------------------------

	EXPORT	__ENTRY
__ENTRY

;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors are read at address 0.
;- They absolutely requires to be in relative addresssing mode in order to 
;- guarantee a valid jump. For the moment, all are just looping (what may be 
;- dangerous in a final system). If an exception occurs before remap, this 
;- would result in an infinite loop. 
;------------------------------------------------------------------------------
                B           InitReset       	; reset
undefvec
                B           undefvec        	; Undefined Instruction
swivec
                B           swivec         		; Software Interrupt
pabtvec
                B           pabtvec         	; Prefetch Abort
dabtvec 
                B           dabtvec         	; Data Abort
rsvdvec
                B           rsvdvec         	; reserved
irqvec
                B			IRQ_Handler_Entry 	; IRQ : read the AIC
fiqvec
;------------------------------------------------------------------------------
;- Function             : FIQ_Handler_Entry
;- Treatments           : FIQ Controller Interrupt Handler.
;- Called Functions     : AIC_FVR[interrupt]
;------------------------------------------------------------------------------

FIQ_Handler_Entry

;- Switch in SVC/User Mode to allow User Stack access for C code
; because the FIQ is not yet acknowledged

;- Save and r0 in FIQ_Register
        mov         r9,r0
	    ldr         r0 , [r8, #AIC_FVR]
        msr         CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
;- Save scratch/used registers and LR in User Stack
        stmfd       sp!, { r1-r3, r12, lr}

;- Branch to the routine pointed by the AIC_FVR
        mov         r14, pc
        bx          r0

;- Restore scratch/used registers and LR from User Stack
        ldmia       sp!, { r1-r3, r12, lr}

;- Leave Interrupts disabled and switch back in FIQ mode
        msr         CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ

;- Restore the R0 ARM_MODE_SVC register
        mov         r0,r9

;- Restore the Program Counter using the LR_fiq directly in the PC
        subs        pc,lr,#4


;--------------------
;- The reset handler
;--------------------
InitReset

;-------------------------------------
;- Setup the stack for supervisor mode
;-------------------------------------
	ldr     sp, =0x204000	; Init stack SVC

;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;----------------------------------------------------------------------

	IMPORT     AT91F_LowLevelInit

	ldr       r0, = AT91F_LowLevelInit
	mov       lr, pc
	bx        r0

;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ management.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be definehere.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;------------------------------------------------------------------------------

;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Interrupt and Supervisor Stack are located at the top of internal memory in
;- order to speed the exception handling context saving and restoring.
;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------

IRQ_STACK_SIZE          EQU     (3*8*4)     ; 3 words per interrupt priority level

ARM_MODE_FIQ            EQU     0x11
ARM_MODE_IRQ            EQU     0x12
ARM_MODE_SVC            EQU     0x13

I_BIT                   EQU     0x80
F_BIT                   EQU     0x40

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
                ldr     r0, =0x204000

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
;- Init the FIQ register
            	ldr     r8, =AT91C_BASE_AIC

;- Set up Interrupt Mode and set IRQ Mode Stack
                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack IRQ
                sub     r0, r0, #IRQ_STACK_SIZE

;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
                msr     CPSR_c, #ARM_MODE_SVC
                mov     r13, r0
                
;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------
;- Following labels are automatically generated by the linker. 
;- RO: Read-only = the code
;- RW: Read Write = the data pre-initialized and zero-initialized.
;- ZI: Zero-Initialized.
;- Pre-initialization values are located after the code area in the image.
;- Zero-initialized datas are mapped after the pre-initialized.
;- Note on the Data position : 
;- If using the ARMSDT, when no -rw-base option is used for the linker, the 
;- data area is mapped after the code. You can map the data either in internal
;- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
;- Note also that to improve the code density, the pre_initialized data must 
;- be limited to a minimum.
;------------------------------------------------------------------------------

	add     r2, pc,#-(8+.-CInitData)  ; @ where to read values (relative)
	ldmia   r2, {r0, r1, r3} ; , r4}
	
	cmp         r0, r1                  ; Check that they are different
	beq         EndRW
LoopRW	
	cmp         r1, r3                  ; Copy init data
	ldrcc       r2, [r0], #4
	strcc       r2, [r1], #4
	bcc         LoopRW
EndRW

	mov         r2, #0
LoopZI	
	cmp         r3, r4                  ; Zero init
	strcc       r2, [r3], #4
	bcc         LoopZI
 
	b           EndInitC
                
CInitData
 	IMPORT      |Image$$FLASH_RO$$Limit| ; End of SRAM code (=start of ROM data)
	IMPORT      |Image$$SRAM_RW$$Base|   ; Base of RAM to initialise
	IMPORT      |Image$$SRAM_ZI$$Base|   ; Base and limit of area
	IMPORT      |Image$$SRAM_ZI$$Limit|  ; Top of zero init segment
	
	DCD     |Image$$FLASH_RO$$Limit|     ; End of SRAM code (=start of ROM data)
 	DCD     |Image$$SRAM_RW$$Base|       ; Base of RAM to initialise
 	DCD     |Image$$SRAM_ZI$$Base|       ; Base and limit of area
 	DCD     |Image$$SRAM_ZI$$Limit|      ; Top of zero init segment
EndInitC

;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb 
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors 
;------------------------------------------------------------------------------
	IMPORT      __main

	ldr       r0, =__main
	mov       lr, pc
	bx        r0

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
	b           End
		
;------------------------------------------------------------------------------
;- Manage exception
;---------------
;- This module The exception must be ensure in ARM mode
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;- Function             : IRQ_Handler_Entry
;- Treatments           : IRQ Controller Interrupt Handler.
;- Called Functions     : AIC_IVR[interrupt] 
;------------------------------------------------------------------------------

IRQ_Handler_Entry

;- Manage Exception Entry
;- Adjust and save LR_irq in IRQ stack
            sub         lr, lr, #4
            stmfd       sp!, {lr}
;- Save and r0 in IRQ stack
            stmfd       sp!, {r0}

;- Write in the IVR to support Protect Mode
;- No effect in Normal Mode
;- De-assert the NIRQ and clear the source in Protect Mode
            ldr         r14, =AT91C_BASE_AIC
	    ldr         r0 , [r14, #AIC_IVR]
	    str         r14, [r14, #AIC_IVR]

;- Enable Interrupt and Switch in Supervisor Mode
           msr         CPSR_c, #ARM_MODE_SVC

;- Save scratch/used registers and LR in User Stack
            stmfd       sp!, { r1-r3, r12, r14}

;- Branch to the routine pointed by the AIC_IVR
            mov         r14, pc
            bx          r0

;- Restore scratch/used registers and LR from User Stack
            ldmia       sp!, { r1-r3, r12, r14}

;- Disable Interrupt and switch back in IRQ mode
            msr         CPSR_c, #I_BIT :OR: ARM_MODE_IRQ

;- Mark the End of Interrupt on the AIC
            ldr         r14, =AT91C_BASE_AIC
            str         r14, [r14, #AIC_EOICR]

;- Restore SPSR_irq and r0 from IRQ stack
            ldmia       sp!, {r0}

;- Restore adjusted  LR_irq from IRQ stack directly in the PC
            ldmia       sp!, {pc}^

;------------------------------------------------------------------------------
;- Manage exception
;---------------
;- The exception must be ensure in ARM mode
;------------------------------------------------------------------------------

	EXPORT AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler
            b     AT91F_Default_FIQ_handler


    EXPORT AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler
            b     AT91F_Default_IRQ_handler

	EXPORT AT91F_Spurious_handler
AT91F_Spurious_handler
            b     AT91F_Spurious_handler

;------------------------------------------------------------------------------
;- Function             : disable_interrupt
;------------------------------------------------------------------------------
	EXPORT AT91F_disable_interrupt

AT91F_disable_interrupt

	MRS r0, CPSR
    ORR r0, r0, #0x80
    MSR CPSR_c, r0

	BX	r14

;------------------------------------------------------------------------------
;- Function             : enable_interrupt
;------------------------------------------------------------------------------
	EXPORT AT91F_enable_interrupt

AT91F_enable_interrupt

    MRS r0, CPSR
    BIC r0, r0, #0x80
    MSR CPSR_c, r0

	BX	r14
	
	END