📄 lan91c111end.h
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#define BANK3_MGMT 8 /* PHY management */
#define BANK3_REV 10 /* Chip Id/Revision */
#define BANK3_ERCV 12 /* Early receive configuration */
/* Masks for Transmit Control Register (BANK0_TCR) */
#define TCR_FDSE 0x8000 /* Full Duplex Switched Ethernet */
/*#define TCR_ETEN_TYPE 0x4000*/ /* Early Tx Underrun Function Type */
#define TCR_EPH_LOOP 0x2000 /* Loop at EPH block */
#define TCR_STP_SQET 0x1000 /* Stop xmit on SQET error */
#define TCR_FDX 0x0800 /* Full duplex mode */
#define TCR_MON_CSN 0x0400 /* Monitor carrier */
#define TCR_NO_CRC 0x0100 /* Don't append CRC */
#define TCR_PAD_EN 0x0080 /* Pad short frames */
/*#define TCR_TXPEN 0x0008*/ /* Enable Pause Frame FC */
#define TCR_FOR_COL 0x0004 /* Force collision */
#define TCR_LOOP 0x0002 /* Local loopback */
#define TCR_TX_ENA 0x0001 /* Enable transmitter */
/* Masks for Receive Control Register (BANK0_RCR) */
#define RCR_RESET 0x8000 /* Software reset */
#define RCR_FILT_CAR 0x4000 /* Filter carrier for 12 bits */
#define RCR_ABRT_ENB 0x2000 /* Abort Receive When Collosions Occur*/
/*#define RCR_GAIN 0x0c00*/ /* Adjust pll gain (test only) */
#define RCR_STRP_CRC 0x0200 /* Strip CRC on received frames */
#define RCR_RX_EN 0x0100 /* Enable receiver */
#define RCR_ALL_MUL 0x0004 /* Accept all multicasts (no filtering) */
#define RCR_PRMS 0x0002 /* Promiscuous mode */
#define RCR_ABORT 0x0001 /* Frame aborted (too long) */
/* Masks for Counter Register (BANK0_CTR) */
#define CTR_EX_DFER 0xf000 /* Number of excessively deferred xmits */
#define CTR_DFER 0x0f00 /* Number of deferred xmits */
#define CTR_MCOL 0x00f0 /* Number of multiple collisions */
#define CTR_COL 0x000f /* Number of single collisions */
/* Masks for Memory Information Register (BANK0_MIR) */
#define MIR_FREE_MEM 0xff00 /* Memory available (* 256 bytes) */
#define MIR_MEM_SIZE 0x00ff /* Memory size (* 256 bytes) */
/* Memory Configuration Register (BANK0_MCR) */
#define MCR_RES_XMIT 0x00ff /* Memory reserved for xmit (* 256 bytes) */
#define MCR_FACTOR 0x0e00 /* Memory size multiplier */
/* Adapter Configuration Register (BANK1_CONFIG) */
#if 0
#define CFG_SELECT 0x8000 /* =1 100mb port, =0 10mb port */
#define CFG_NO_WAIT 0x1000 /* No wait states */
#define CFG_FULL_STEP 0x0400 /* Full step signalling to AUI */
#define CFG_SETSQLCH 0x0200 /* Set squelch level */
#define CFG_AUI_SEL 0x0100 /* =1 AUI, =0 twisted pair transeiver */
#define CFG_16BIT 0x0080 /* System bus width */
#define CFG_DIS_LINK 0x0040 /* Disable link test functions (10BASET) */
#define CFG_RAM_SZ 0x0020 /* =0 8kb, =1 32kb */
#define CFG_RAM_WDTH 0x0010 /* =0 8 bit, =1 16 bit */
#define CFG_FAST_RAM 0x0008 /* SRAM timing */
#define CFG_MASK_IRQ 0x0006 /* IRQ used =0 IRQ9 */
/* =1 IRQ3 */
/* =2 IRQA */
/* =3 IRQB */
#endif
/* Base Address Register (BANK1_BASE) */
#define BASE_IO_ADR 0xff00 /* Mask IO base address (a15,a14,a13,a9,a8,a7,a6,a5) */
/* All others MBZ */
#define BASE_ROM_SZ 0x00c0 /* ROM size =0 Disabled */
/* =1 16kb */
/* =2 32kb */
/* =3 64kb */
#define BASE_ROM_ADR 0x003e /* ROM address decode */
/* Configuration Control Register (BANK1_CTL) */
/*#define CTL_BYPASS 0x8000*/ /* Bypass MMU */
#define CTL_RCV_BAD 0x4000 /* Receive bad CRC packets */
/*#define CTL_PWR_DOWN 0x2000*/ /* Enter powerdown mode */
#define CTL_AUTO 0x0800 /* Auto-release xmit memory */
/*#define CTL_UDOE 0x0100*/ /* User data output enable */
#define CTL_LE_EN 0x0080 /* Link error enable (mux into EPH int) */
#define CTL_CR_EN 0x0040 /* Counter rollover enable (mux into EPH int) */
#define CTL_TE_EN 0x0020 /* Xmit error enable (mux into EPH int) */
#define CTL_EEPROM 0x0004 /* EEPROM select */
#define CTL_RELOAD 0x0002 /* Reload from EEPROM */
#define CTL_STORE 0x0001 /* Store to EEPROM */
/* MMU Command Register (BANK2_MMU_CMD) */
#define MMUCMD_MSK 0x00e0 /* Mask out command */
#define MMUCMD_MEM_SZ 0x0007 /* Mask size of request (if cmd = alloc) */
/* amount = (value + 1) * 256 bytes */
#define MMUCMD_BUSY 0x0001 /* MMU busy don't mod PNR */
/* MMU Commands */
#define CMD_NOP 0 /* No-Op command */
#define CMD_ALLOC 0x0020 /* Allocate memory */
#define CMD_RIS 0x0040 /* Reset to initial state */
#define CMD_REM_TOP 0x0060 /* Remove frame from top of RX fifo */
/*#define CMD_REM_TXFIFO 0x0070*/ /* Remove top of TX fifo to Tx Completion Fifo */
#define CMD_REM_REL_TOP 0x0080 /* Remove and release top of RX fifo */
#define CMD_REL_SPEC 0x00a0 /* Release specific packet */
#define CMD_ENQ_TX 0x00c0 /* Enqueue to xmit fifo */
#define CMD_ENQ_RX 0x00e0 /* Reset xmit fifos (should only be done */
/* with transmitter disabled) */
/* Allocation Result Register (BANK2_ARR) This is an 8 bit register */
#define ARR_FAIL 0x80 /* Allocation failed */
#define ARR_ALLOC_MSK 0x7f /* Mask allocated packet number */
/* Actually 1fh but use full mask for */
/* upward compatibility. */
/* Fifo Port Registers (BANK2_TX_FIFO, BANK2_RX_FIFO) These are 8 bit registers */
#define FIFO_EMPTY 0x80 /* No packet at top of fifo */
/* PG 10-15-99 */
#define FIFO_RX_EMPTY 0x8000
#define FIFI_MASK 0x7f /* Mask top packet number */
/* Actually 1fh but use full mask for */
/* upward compatibility. */
/* Pointer Register (BANK2_PTR) */
#define PTR_RCV 0x8000 /* Access is to receive area */
#define PTR_AUTO 0x4000 /* Auto-increment on access */
#define PTR_READ 0x2000 /* =1 then read operation */
/* =0 then write operation */
#define PTR_ETEN 0x1000 /* Detect early transmit underrun */
/*#define PTR_AUTO_TX 0x0800*/ /* Write fifo not empty */
#define PTR_NOT_EMPTY 0x0800 /* Write fifo not empty */
#define PTR_OFFSET 0x03ff /* Mask pointer value */
/* Interrupt Registers (BANK2_INT_STS, BANK2_INT_ACK, BANK2_INT_MSK) */
#define INT_TX_IDLE 0x80 /* Xmit IDLE interrupt */
/* PG added for 91c111 12/22/00 */
#define INT_MDINT 0x80 /* 91C111 MDINT interrupt */
#define INT_EARLY_RX 0x40 /* Early receive */
#define INT_EPH_INT 0x20 /* EPH type interrupt */
#define INT_RX_OVRN 0x10 /* Receive overrun interrupt */
#define INT_ALLOC 0x08 /* Allocation interrupt */
#define INT_TXF_EMPTY 0x04 /* Xmit fifo empty interrupt */
#define INT_TX_CMP 0x02 /* Xmit complete interrupt */
#define INT_RX_CMP 0x01 /* Receive complete interrupt */
#define NUMBER_INTS 7 /* Number of possible bits in the mask */
#define ENABLED_INTS (INT_MDINT | INT_TX_CMP | INT_RX_CMP | INT_EPH_INT | INT_RX_OVRN )
/* Isolate packet number in PNR */
#define PNR_MASK 0x7f
/* Management Interface Register (BANK3_MGMT) */
#define MGMT_MDOE 0x0008 /* Output enable */
#define MGMT_MCLK 0x0004 /* Drive MDCLK */
#define MGMT_MDI 0x0002 /* Read MDI pin */
#define MGMT_MDO 0x0001 /* Write MDO pin */
/* Revision Register (BANK3_REV) */
#define REV_CHIP_ID 0x00f0 /* Mask chip ID */
#define REV_REV_ID 0x000f /* Mask chip revision. */
#define CHIP_ID_92 3 /* Chip is 91C92 */
#define CHIP_ID_94 4 /* Chip is 91C94 */
#define CHIP_ID_100 7 /* Chip is 91C100 (FEAST) */
/* RK 970306 */
#define CHIP_ID_95 5 /* Chip is 91C95 */
#define REV_CHIP_ID_96 6 /* Chip is 91C96 */
#define CHIP_ID_100FD 8 /* Chip is 91C100FD (FEAST FD) */
#define CHIP_ID_110FD 9 /* Chip is 91c110FD */
/* Early Receive Register (Bank3_Ercv) */
#define ERCV_DISCARD 0x0080 /* Discard packet being received */
#define ERCV_THRESHOLD 0x001f /* Threshold for ERCV-INT in 64 byte units */
BOOLEAN Ositech;
/* Hardware packet representation. */
typedef struct _SMC_PACK_HEADER
{
USHORT Status;
USHORT Range;
} SMC_PACK_HEADER;
#define SMC_PACK_HEADER_SIZE sizeof(SMC_PACK_HEADER)
/*OSITECH++ */
#define CCR_MEMORY_OFFSET (0x0400)
#define NET_CCR_OFFSET (0x00)
#define MODEM_CCR_OFFSET (0x20)
/* OSITECH-- */
/* Dual function card attribute memory representation. */
typedef struct _DUAL_ATTRIBUTE_MEMORY
{
UCHAR EthernetOption;
UCHAR Reserved1;
UCHAR EthernetStatus;
UCHAR Reserved2;
UCHAR Unused1[6];
UCHAR LanPortLo;
UCHAR Reserved3;
UCHAR LanPortHi;
UCHAR Reserved4;
UCHAR Unused2[18];
UCHAR ModemOption;
UCHAR Reserved5;
UCHAR ModemStatus;
UCHAR Reserved6;
UCHAR Pin;
UCHAR Reserved7;
UCHAR Unused3[2];
UCHAR Event;
UCHAR Reserved8;
UCHAR ModemPortLo;
UCHAR Reserved9;
UCHAR ModemPortHi;
UCHAR Reserved10;
} DUAL_ATTRIBUTE_MEMORY;
typedef struct
{
int len;
UCHAR * pData;
} RX_PKT; /* received packet */
typedef struct
{
M_BLK_ID pMblk;
} TX_PKT; /* transmit packet */
#define DUAL_ATTRIBUTE_MEMORY_SIZE sizeof(DUAL_ATTRIBUTE_MEMORY)
#define TX_PACKETS 0x8
#define RX_PACKETS 0x8
/* Masks for dual function PCMCIA card OPTION register.*/
#define SRESET 0x80 /* Reset function. */
#define LEV_IRQ 0x40 /* Level mode interrupts. */
#define DISABLE_EEPROM 0x08 /* Disable EEPROM usage. */
#define ENABLE_IRQ 0x04 /* Enable function interrupts. */
#define ENABLE_BASE 0x02 /* Enable I/O decoder. */
#define ENABLE_FUNCTION 0x01 /* Enable function. */
/* Masks for dual function PCMCIA card STATUS register. */
#define IO8 0x20 /* Only 8-bit I/O from host. */
#define POWER_DOWN 0x04 /* Enter power-down mode.*/
#define INTERRUPT_ACTIVE 0x02 /* Function is interrupting. */
#define INTERRUPT_ACK 0x01 /* Acknowledge interrupt.*/
/*OSITECH++ */
#define MODEM_AUDIO 0x08
/* OSITECH-- */
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