📄 lan91c111end.h
字号:
/* lan91c111End.h - header file for END style LAN91C111 ethernet chip */
/*
modification history
--------------------
01a,10apr00,ab written
*/
#ifndef __INClan91c111Endh
#define __INClan91c111Endh
#ifdef __cplusplus
extern "C" {
#endif
/* basic macros starts here */
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef NULL
#define NULL '\0' /* Null pointer */
#endif
#define CDECL _cdecl
#define PASCAL _pascal
#define VOID void
#define CONST const
#define VOLATILE volatile
typedef int INT;
/* typedef unsigned int UINT; */
typedef int BOOLEAN;
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
#ifndef _H2INC
typedef struct qword_s { /* qword */
DWORD qword_lo;
DWORD qword_hi;
} QWORD;
#endif
typedef char CHAR;
/* typedef unsigned char UCHAR; */
typedef short SHORT;
/* typedef unsigned short USHORT; */
typedef long LONG;
/* typedef unsigned long ULONG; */
typedef VOID *PVOID;
typedef PVOID *PPVOID;
typedef INT *PINT;
typedef UINT *PUINT;
typedef BYTE *PBYTE;
typedef WORD *PWORD;
typedef DWORD *PDWORD;
typedef CHAR *PCHAR;
typedef SHORT *PSHORT;
typedef LONG *PLONG;
typedef UCHAR *PUCHAR;
typedef USHORT *PUSHORT;
typedef ULONG *PULONG;
typedef BOOL *PBOOL;
typedef UCHAR SZ[];
typedef UCHAR *PSZ;
typedef UCHAR SZZ[];
typedef UCHAR *PSZZ;
typedef USHORT SEL;
typedef SEL *PSEL;
typedef ULONG PPHYS;
typedef (*PFN)();
typedef PFN *PPFN;
typedef PVOID HANDLE;
typedef HANDLE *PHANDLE;
typedef ULONG HTIMEOUT;
typedef ULONG CMS;
#ifndef NOMINMAX
#ifndef max
#define max(a,b) (((a) > (b)) ? (a) : (b))
#endif
#ifndef min
#define min(a,b) (((a) < (b)) ? (a) : (b))
#endif
#endif /* NOMINMAX */
#define MAKEWORD(a, b) ((WORD)(((BYTE)(a)) | ((WORD)((BYTE)(b))) << 8))
#define MAKELONG(a, b) ((LONG)(((WORD)(a)) | ((DWORD)((WORD)(b))) << 16))
#define LOWORD(l) ((WORD)(l))
#define HIWORD(l) ((WORD)(((DWORD)(l) >> 16) & 0xFFFF))
#define LOBYTE(w) ((BYTE)(w))
#define HIBYTE(w) ((BYTE)(((WORD)(w) >> 8) & 0xFF))
/* card specific macros starts here */
#if 0
#define SMC_CODE 0x0108
#define SMC_REV 0x0133
#define SMC_REV2 0x0201
#endif
#define MANUFACTURE_ID 0x20
#define LAN_FUNC 0x22
#define LAN_NODEID 0x04
/* Buffer and frame management constants. */
#define MAX_FRAME_SIZE ((USHORT)1514)
#define MIN_FRAME_SIZE 14
#define MIN_LEGAL_FRAME_SIZE 64
#define ETHERNET_HEADER_SIZE 14
#define MAX_LOOKAHEAD_SIZE 1500
#define MIN_LOOKAHEAD_SIZE 256
#define LOOK_AHEAD_BUFFER_SIZE 2048
#define DOUBLE_BUFFER_SIZE 2048
#define MAX_FRAME_DATA_SIZE 1500
#define MAX_MULTICAST_ADDRESS 128
#define BAD_IO_BASE 0x1c1f /* If any bits on then invalid io address */
#define BAD_MODEM_BASE 0x7 /* If any bits on then invalid io address */
#define RESET_TIME 16 /* How long to hold reset */
#define FRAME_OVERHEAD 6 /* Overhead bytes for adapter control */
#define RANGE_MASK 0x7ff /* Mask range provided by adapter */
#define MAX_ERRORS 10 /* Error ceiling before adapter check */
#define MMU_WAIT 2000 /* Loop count waiting for memory allocation */
#define PTR_WAIT 5 /* Loop count waiting after pointer load */
#define BANK_SELECT 14 /* Offset in IO space to Bank select */
#define BOARD_ADDRESS 0x20 /* Offset to ROM card address */
#define BANK_ID_MASK 0xff00 /* Mask constant part of bank register */
#define BANK_UPPER 0x3300 /* Constant value for upper byte of bank register */
#define BANK_MASK (BANK_UPPER | 3)
#define ATTRIBUTE_MEMORY_LENGTH 0x1000 /* PCMCIA attribute memory size */
#define RESOURCE_LIST_SIZE 256 /* Multifunction resource list. */
#define CHECK_TIMER_INTERVAL 5000
#define TRANSMIT_CHECK_INTERVAL 100
/* Driver - Adapter defaults. */
#define DEFAULT_IO_BASE 0x300 /* Default base address */
#define DEFAULT_IRQ 9 /* Default interrupt level */
#define DEFAULT_MEDIA 0 /* Default media type */
#define DEFAULT_LOOK_AHEAD MAX_LOOKAHEAD_SIZE
#define DEFAULT_SMC_CONFIG 0x1086 /* default SMC config register */
#define MILLISECOND 1000 /* in microseconds */
#if 0
#define MODEM 1
#define LAN 2
#define LANMODEM 3
#endif
/* 9000 derivative type definitions. We need an established order */
/* to these so we can do greater-than, less-than testing. */
typedef enum _SMC_CARD_TYPES
{
CARD_UNKNOWN,
CARD_SMC9000,
CARD_SMC91C92,
CARD_SMC91C94,
CARD_SMC91C96,
CARD_SMC91C100,
CARD_SMC91C100FD,
CARD_SMC91C110,
CARD_SMC91C111
} SMC_CARD_TYPES;
/* Frame send/receive control byte */
#define CTL_BYTE_ODD 0x20 /* Frame ends on odd byte boundary */
#define CTL_BYTE_CRC 0x10 /* Append CRC on xmit */
/* Receive frame status word */
#define RFS_ALIGN 0x8000 /* Frame alignment error */
#define RFS_BCAST 0x4000 /* Frame was broadcast */
#define RFS_CRC 0x2000 /* Frame CRC error */
#define RFS_ODD 0x1000 /* Frame has odd byte count */
#define RFS_LONG 0x0800 /* Frame was too long */
#define RFS_SHORT 0x0400 /* Frame was too short */
#define RFS_MCAST 0x0001 /* Frame was multicast */
#define RFS_HASH 0x00fe /* Mask hash value (multicast) */
#define RFS_ERROR (RFS_ALIGN | RFS_CRC | RFS_LONG | RFS_SHORT)
/* Transmit frame status word (Same masks used for EPH status register) */
#define TFS_UNDERRUN 0x8000 /* Frame uderrun */
#define TFS_LINKERROR 0x4000 /* 10BASET link error condition */
/*#define TFS_RXOVERRUN 0x2000*/ /* Receiver overrun */
#define TFS_COUNTER 0x1000 /* Counter roll over */
#define TFS_EXDEFER 0x0800 /* Excessive deferral */
#define TFS_CARRIER 0x0400 /* Carrier not present */
#define TFS_LATE 0x0200 /* Late collision */
#define TFS_DEFER 0x0080 /* Frame was deferred */
#define TFS_BCAST 0x0040 /* Last frame was broadcast */
#define TFS_SQET 0x0020 /* Signal Quality Error */
#define TFS_16COL 0x0010 /* Too many collisions */
#define TFS_MCAST 0x0008 /* Last frame was multicast */
#define TFS_MULTICOL 0x0004 /* Multiple collisions on last frame */
#define TFS_1COL 0x0002 /* Single collision on last frame */
#define TFS_OKAY 0x0001 /* Frame successfully transmitted */
#define TFS_ERROR (TFS_UNDERRUN | TFS_EXDEFER | TFS_CARRIER | TFS_LATE | TFS_16COL)
/* Bank 0 Registers */
#define BANK0_TCR 0 /* Transmit control register */
#define BANK0_STS 2 /* EPH status register */
#define BANK0_RCR 4 /* Receive control register */
#define BANK0_CTR 6 /* Statistics counter register */
#define BANK0_MIR 8 /* Memory information register */
#define BANK0_MCR 10 /* Memory configuration register */
#define BANK0_RPCR 10 /* Memory configuration register */
#define BANK0_RES 12 /* Reserved */
/* Bank 1 Registers */
#define BANK1_CONFIG 0 /* Adapter configuration register */
#define BANK1_BASE 2 /* IO Base address */
#define BANK1_IA0 4 /* Current address bytes 0-1 */
#define BANK1_IA2 6 /* Current address bytes 2-3 */
#define BANK1_IA4 8 /* Current address bytes 4-5 */
#define BANK1_GEN 10 /* General purpose */
#define BANK1_CTL 12 /* Control */
/* Bank 2 Registers */
#define BANK2_MMU_CMD 0 /* MMU command register */
#define BANK2_AUTO_TX 1 /* Auto Tx Start Register */
#define BANK2_PNR 2 /* Packet Number Register (8 bit) */
#define BANK2_ARR 3 /* Allocation Result Register (8 bit) */
#define BANK2_FIFOS 4
#define BANK2_TX_FIFO 4 /* Transmit Fifo Port Register (8 bit) */
#define BANK2_RX_FIFO 5 /* Receive Fifo Port Register (8 bit) */
#define BANK2_PTR 6 /* Pointer Register */
#define BANK2_DATA1 8 /* Data Register */
#define BANK2_DATA2 10 /* Data Register */
#define BANK2_INT_STS 12 /* Interrupt Status Register (8 bit, Read Only) */
#define BANK2_INT_ACK 12 /* Interrupt Ack Register (8 bit, Write Only) */
#define BANK2_INT_MSK 13 /* Interrupt Mask Register (8 bit, Read/Write) */
/* Bank 3 Registers */
#define BANK3_MT01 0 /* Multicast Hash Table 0-1 */
#define BANK3_MT23 2 /* Multicast Hash Table 2-3 */
#define BANK3_MT45 4 /* Multicast Hash Table 4-5 */
#define BANK3_MT67 6 /* Multicast Hash Table 6-7 */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -