c

MCF5272的板极初始化程序

/*********************************************************************
 *
 * Copyright:
 *	MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************/

/*
 * File:	mcf5272_lo.s
 * Purpose:	Lowest level routines for mcf5272.
 *
 * Notes:	This file assembles with both Diab and GNU tools
 */

#ifdef _UNDERSCORE_
#define mcf5272_mbar		_mcf5272_mbar
#define exception_handler	_exception_handler
#define mcf5272_rambar		_mcf5272_rambar
#define mcf5272_init		_mcf5272_init
#define main				_main
#endif
 
	.extern ___SP_INIT
	.extern exception_handler
	.extern mcf5272_mbar
	.extern mcf5272_rambar
	.extern mcf5272_init
	.extern main

	.global asm_startmeup
	.global _asm_startmeup

	.global	asm_exception_handler
	.global	_asm_exception_handler
	.global	asm_set_ipl
	.global	_asm_set_ipl
	.global cpu_cache_flush
	.global _cpu_cache_flush
	.global	mcf5272_wr_vbr
	.global _mcf5272_wr_vbr
	.global	mcf5272_wr_cacr
	.global _mcf5272_wr_cacr
	.global	mcf5272_wr_acr0
	.global _mcf5272_wr_acr0
	.global	mcf5272_wr_acr1
	.global _mcf5272_wr_acr1
	.global	mcf5272_wr_rambar
	.global _mcf5272_wr_rambar
	.global	mcf5272_wr_mbar
	.global _mcf5272_wr_mbar
	.global	mcf5272_wr_sr
	.global _mcf5272_wr_sr
	.global mcf5272_wr_movem_line
	.global _mcf5272_wr_movem_line

	.equ	SRAMsize,4096	/* 4K Byte SRAM, organized as 1K * 32 bits */

	.text

/********************************************************************
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:

	/* Invalidate the cache and disable it */
	move.l	#0x01000000,d0                  //d0=0x01000000
	movec	d0,cacr                         //CASR清零（初始化）

	/* Disable ACRs */
	moveq.l	#0,d0
	movec	d0,ACR0
	movec	d0,ACR1

	/* Initialize SRAMBAR: locate SRAM and validate it */
	move.l	#0xE0000021,d0
	movec	d0,RAMBAR

	/*
	 * Point SP into SRAM (temporarily).  SRAM is used as stack space
	 * while initializing the mcf5272 periphs and memory controller.
	 */
	move.l	#0xE0000000+SRAMsize,SP

	/* Obtain pointer to where MBAR is to be mapped */
	jsr		mcf5272_mbar
	move.l	d0,d6

	/* Obtain pointer to where RAMBAR is to be mapped */
	jsr		mcf5272_rambar

	/* Adjust SP to (soon to be valid) SRAM */
	move.l	d0,a0
	lea		SRAMsize(a0),SP

	/* Map RAMBAR and MBAR */
	ori.l	#0x21,d0			/* Set Valid and C/I bit */
	movec	d0,RAMBAR

	move.l	d6,d0
	addq.l	#1,d0				/* Set Valid bit */
	movec	d0,MBAR

	/* Initialize mcf5272 periphs, etc */
	move.l	d6,-(sp)			/* pointer to internal resources */
	jsr		mcf5272_init
	lea		4(sp),sp

	/* Point SP to SDRAM */
	move.l	#___SP_INIT,sp

	nop

	jmp		main

	halt

/********************************************************************
 * mcf5272 has Icache only
 */
cpu_cache_flush:
_cpu_cache_flush:
	nop						/* sync */
	move.l	#0x01000000,d0	/* Invalidate the I-Cache */
	movec d0,cacr
	rts

/********************************************************************
/*
 * This routine is the lowest-level exception handler.
 */
asm_exception_handler:
_asm_exception_handler:

	move.l	(sp),a1
	move.l	a1,-(sp)
	jsr		exception_handler
	lea		4(sp),sp
	rte

/********************************************************************
/*
 * This routines changes the IPL to the value passed into the routine.
 * It also returns the old IPL value back.
 * Calling convention from C:
 *   old_ipl = asm_set_ipl(new_ipl);
 * For the Diab Data C compiler, it passes return value thru D0.
 * Note that only the least significant three bits of the passed
 * value are used.
 */

asm_set_ipl:
_asm_set_ipl:
	link	a6,#-8
	movem.l	d6-d7,(sp)

	move.w	sr,d7		/* current sr	 */

	move.l	d7,d0		/* prepare return value	 */
	andi.l	#0x0700,d0	/* mask out IPL	 */
	lsr.l	#8,d0		/* IPL	 */

	move.l	8(a6),d6	/* get argument	 */
	andi.l	#0x07,d6		/* least significant three bits	 */
	lsl.l	#8,d6		/* move over to make mask	 */

	andi.l	#0x0000F8FF,d7	/* zero out current IPL	 */
	or.l	d6,d7			/* place new IPL in sr	 */
	move.w	d7,sr

	movem.l	(sp),d6-d7
	lea		8(sp),sp
	unlk	a6
	rts

/********************************************************************
 * These routines write to the special purpose registers in the ColdFire
 * core.  Since these registers are write-only in the supervisor model,
 * no corresponding read routines exist.
 */
mcf5272_wr_vbr:
_mcf5272_wr_vbr:
	move.l	4(sp),d0
	andi.l	#0xFFF00000,d0	/* align to 1M boundary	 */
	movec	d0,VBR
	nop
	rts

mcf5272_wr_cacr:
_mcf5272_wr_cacr:
    move.l  4(sp),d0
    movec d0,cacr
    nop
    rts

mcf5272_wr_acr0:
_mcf5272_wr_acr0:
    move.l  4(sp),d0
    movec d0,ACR0
    nop
    rts

mcf5272_wr_acr1:
_mcf5272_wr_acr1:
    move.l  4(sp),d0
    movec d0,ACR1
    nop
    rts

mcf5272_wr_rambar:
_mcf5272_wr_rambar:
    move.l  4(sp),d0
    movec d0,RAMBAR
    nop
    rts

mcf5272_wr_mbar:
_mcf5272_wr_mbar:
    move.l  4(sp),d0
    movec d0,MBAR
    nop
    rts
    
mcf5272_wr_sr:
_mcf5272_wr_sr:
	move.l	4(sp),d0
	move.w	d0,SR
	rts

#ifndef __MWERKS__

/*  .init section */
	section	.init$00,2,C
	XDEF	___init		; Entry to ___init, called by
___init:			; ___init_main called above.

	; Linker places .init sections from other modules, containing
	; calls to initialize global objects, here.

	section	.init$99,2,C
	rts			; Return from ___init.

/* .fini section */
	section	.fini$00,2,C
	XDEF	___fini
___fini:			; Entry to ___fini, called by exit().

	; Linker places .fini sections from other modules, containing
	; calls to destroy global objects, here.

	section	.fini$99,2,C
	rts			; Return from ___fini.

#endif

	.end