c5_4_3.asm

《DSP应用开发实用子程序》书中所有例程

            	.def start
            	.def ad
            	.def ad_start
            	.def rpt,timer1
           	    .ref ftranform
            	.ref sinx
              
tim1_ctl    	.equ  0x01980000			
tim1_prd    	.equ  0x01980004			
tim1_cnt    	.equ  0x01980008			
ce3ctl      	.equ  0x01800014			
ce1ctl      	.equ  0x01800004			
pcr         	.equ  0x018c0024 			
pcr1        	.equ  0x01900024 			
            
            	.bss 	 reg,128,0,0			
            	.global reg    				

            	.sect 	 ".boot"			
start:
            mvk	     ce1ctl,b0				
            mvkh 	 ce1ctl,b0
            mvkl 	 0ffffff0fh,a0
            mvkh  	 0ffffff0fh,a0
            stw  	 a0,*b0
            nop  	 4
            
            mvkl 	 90000400h,b0			
            mvkh 	 90000400h,b0			
            mvkl 	 400h,b1
            mvkh 	 400h,b1
            mvkl 	 9c00h,b2
            mvkh 	 9c00h,b2
pg:            
            ldb  	*b0++,a0			
            nop  	4
            stb  	a0,*b1++
            nop  	3
            sub  	b2,4,b2
            nop  	5
            b     ad_start				
            nop   5
            
            .text
ad_start:   mvc 	csr,b0				
            and 	-2,b0,b0
            mvc 	b0,csr     			
            
            mvkl 	0fff0h,b0
            mvkh 	0fff0h,b0
            mvc 	 b0,icr
            nop            				
            
            mvkl 	pcr,a10
            mvkh	pcr,a10				
            mvkl 	3a2ah,b10   			
            stw  	b10,*a10
            nop  	8
            nop  	4
            
            mvkl  	ce3ctl,a0			
            mvkh  	ce3ctl,a0
            mvkl  	10510222h,a1
            mvkh  	10510222h,a1
            stw   	a1,*a0
            nop   	4            
            
            mvkl 	8020h,b1		
            mvkh 	8020h,b1            
            mvc 	ier,b0
            or  	b1,b0,b0
            mvc 	b0,ier    		
            
            mvc 	ier,b0			
            mvk 	02h,b1
            or  	b1,b0,b0
            mvc 	b0,ier     		
           
timer1_init:   MVKL   tim1_prd, B4		
            MVKH   tim1_prd, B4
            MVKL   02F40h, A0
            ;MVKL   0F40h, A0
            STW     A0, *B4
            NOP     4            		
            
            MVKL   	00000FF7Eh,A2		
            MVKH 	00000FF7Eh,A2
            MVKL 	tim1_ctl, B4
            MVKH 	tim1_ctl, B4
            STW  		A2, *B4
            nop  		4             	
            
cpld:            				
            mvkl 		sinx,b1		
            mvkh 		sinx,b1
            mvkl 		0b0000004h,a1	
            mvkh 		0b0000004h,a1
            
            mvkl		0ffh,a6
            mvkh 		0ffh,a6
            mvkl 		0Fh,b0
            mvkh		0Fh,b0
ad_init:						
      [!b0]  b    		ad_end
            nop  		5
 
            mvkl 		04010000h,a3
            mvkh		 04010000h,a3
            stw  		a3,*a1			
            nop  		3
           
            mvkl 		04000000h,a3
            mvkh 		04000000h,a3
            stw  		a3,*a1			
            nop  		3               	
            
            mvkl		00200000h,a3
            mvkh 		00200000h,a3     	
            stw  		a3,*a1			
            nop  		3
            
            mvkl 		06300000h,a3
            mvkh 		06300000h,a3
            stw  		a3,*a1			
            nop  		3
            
            sub  		b0,1,b0
            
            ldw  		*a1,a11			
            nop  		3
            mvkl 		0230h,a12
            mvkh 		0230h,a12        	
            
            ldw  		*a1,b11			
            nop  		3
            mvkl 		0020h,b12
            mvkh 		0020h,b12       	
            
            shl  		a11,4,a11
            shru 		a11,20,a11
            cmpeq  	a11,a12,a2			
     [!a2]   b    		ad_init			
            nop  		5
            
            shl  		b11,4,b11
            shru 		b11,20,b11
            cmpeq  	b11,b12,b2
     [!b2]   b    		ad_init
            nop  		5
            
            mvkl 		04300000h,a3
            mvkh 		04300000h,a3
            stw  		a3,*a1			
            nop  		3     			
ad_end:      nop  		4   
rpt:          xor 		b0,b0,b0
            mvc 		csr,b0
            or  		1,b0,b0
            mvc 		b0,csr     		
            
            nop  		8
            nop  		8
            
            zero 		a5
            zero 		a2
            
            mvkl 		pcr,a10
            mvkh 		pcr,a10		
            mvkl 		3a28h,b10   	
            stw  		b10,*a10
            nop  		4            
start_time1:   MVKL 	00000FFFEh,A10		
            MVKH	 	00000FFFEh,A10	
            MVKL		tim1_ctl, B10
            MVKH 	tim1_ctl, B10
            STW  		A10, *B10
            nop  		4
loop:       nop
            zero		b0
      [a2]  add 		a5,1,a5
      [a2]  mvkl 		reg,a4
      [a2]  mvkh 		reg,a4
      [a2]  stw  		a5,*a4
      [a2]  b 	 		ftranform       
      	  nop 		5
            nop
            b    		loop
            nop  		5 
ad:          ldw  		*a1,a4
            nop  		4
            shl  		a4,4,a4
            ;shru 		a4,4,a4		
            shr  		a4,4,a4   	
            stw  		a4,*b1++		
            nop  		4
            
            sub  		a6,1,a6  
            cmpeq 		a6,0,a2
               
            b    		irp
            nop  		5
timer1:	   mvkl 		pcr1,a10
            mvkh 		pcr1,a10		
            mvkl 		3a0ah,b10   		
            stw  		b10,*a10
            nop  		8
            nop  		4
            
            mvkl 		3a2ah,b10		
            stw  		b10,*a10
            nop  		8
            nop  		4
            
            mvkl 		3a0ah,b10		
            stw  		b10,*a10
            nop  		4
            
		   mvkl 		ad_start,b0
		   mvkh 		ad_start,b0
            mvc  		b0,irp
            b    		irp
            nop  		5
            .end