mmu.s

ucos2400移植的源码。从网上下载供大家分享。

;****************************************************************************************
;*
;*   	MMU.S - S3C2400 ARM BOARD MMU TABLE
;*
;*		C)	Copyright 2003-3-19 ARM	STUDY	GROUP	(Yoon Gwang-Yoon)
;*		  
;****************************************************************************************
;*	MMU Page Table
;*  	Physical memory map ----> virtual memory map 
;*
;****************************************************************************************
    GBLA    XCount

	AREA    |YGY$$PageTable|, DATA, READONLY, ALIGN=14

	EXPORT  PageTable

PageTable

;========================================================================================
;    	S3C2400 External SDRAM (Bank 6,nGCS6)
;		Cached and Write Buffered
;========================================================================================
    	DCD	0x0c000c1e   ;0x0c00.0000 --> 0x0000.0000	
    	DCD	0x0c100c1e   ;0x0c10.0000 --> 0x0010.0000	
    	DCD	0x0c200c1e   ;0x0c20.0000 --> 0x0020.0000	
    	DCD	0x0c300c1e   ;0x0c30.0000 --> 0x0030.0000	
    	DCD	0x0c400c1e   ;0x0c40.0000 --> 0x0040.0000	
    	DCD	0x0c500c1e   ;0x0c50.0000 --> 0x0050.0000	
    	DCD	0x0c600c1e   ;0x0c60.0000 --> 0x0060.0000	
    	DCD	0x0c700c1e   ;0x0c70.0000 --> 0x0070.0000	
    	DCD	0x0c800c1e   ;0x0c80.0000 --> 0x0080.0000	
    	DCD	0x0c900c1e   ;0x0c90.0000 --> 0x0090.0000	
    	DCD	0x0ca00c1e   ;0x0ca0.0000 --> 0x00a0.0000	
    	DCD	0x0cb00c1e   ;0x0cb0.0000 --> 0x00b0.0000	
    	DCD	0x0cc00c1e   ;0x0cc0.0000 --> 0x00c0.0000	
    	DCD	0x0cd00c1e   ;0x0cd0.0000 --> 0x00d0.0000	
    	DCD	0x0ce00c1e   ;0x0ce0.0000 --> 0x00e0.0000	
    	DCD	0x0cf00c1e   ;0x0cf0.0000 --> 0x00f0.0000		
    	DCD	0x0d000c1e   ;0x0d00.0000 --> 0x0100.0000	
    	DCD	0x0d100c1e   ;0x0d10.0000 --> 0x0110.0000	
    	DCD	0x0d200c1e   ;0x0d20.0000 --> 0x0120.0000	
    	DCD	0x0d300c1e   ;0x0d30.0000 --> 0x0130.0000	
    	DCD	0x0d400c1e   ;0x0d40.0000 --> 0x0140.0000	
    	DCD	0x0d500c1e   ;0x0d50.0000 --> 0x0150.0000	
    	DCD	0x0d600c1e   ;0x0d60.0000 --> 0x0160.0000	
    	DCD	0x0d700c1e   ;0x0d70.0000 --> 0x0170.0000	
    	DCD	0x0d800c1e   ;0x0d80.0000 --> 0x0180.0000	
    	DCD	0x0d900c1e   ;0x0d90.0000 --> 0x0190.0000	
    	DCD	0x0da00c1e   ;0x0da0.0000 --> 0x01a0.0000	
    	DCD	0x0db00c1e   ;0x0db0.0000 --> 0x01b0.0000	
    	DCD	0x0dc00c1e   ;0x0dc0.0000 --> 0x01c0.0000	
    	DCD	0x0dd00c1e   ;0x0dd0.0000 --> 0x01d0.0000	
    	DCD	0x0de00c1e   ;0x0de0.0000 --> 0x01e0.0000	
    	DCD	0x0df00c1e   ;0x0df0.0000 --> 0x01f0.0000	

		;--------------------------------------------------------------------------------
 		;	Dummy 33M~256M   (224M) 0x0200.0000~0x0fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x2200000c
		WHILE	XCount	<	0x30000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

;========================================================================================
; 		S3C2400 Internal Registers
; 		None Cached and Write Buffered
;========================================================================================
		;	Dummy  1M~64M   (64M) 0x1000.0000~0x13ff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x3000000c
		WHILE	XCount	<	0x34000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

		;--------------------------------------------------------------------------------
		;	Register BANK (32M) 0x1400.0000~0x15ff.ffff --> 0x1400.0000~0x15ff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x14000c12
		WHILE	XCount	<	0x16000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

		;--------------------------------------------------------------------------------
		;	Dummy 97M~256M   (160M) 0x1600.0000~0x1fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x3600000c
		WHILE	XCount	<	0x40000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
;    	S3C2400 External FLASH FLASH #1 (Bank 0,nGCS0)
;    	Internal ROM Booting (  4M Byte) , 0x0000.0000 ~ 0x003F.FFFF (Supports HY29LV320)
;    	External ROM Booting (128K Byte) , 0x0000.0000 ~ 0x0001.FFFF (Supports ATF29LV1024)
;		None Cached and Write Buffered
;========================================================================================
    	DCD	0x00000c12   ;0x0000.0000 --> 0x2000.0000	
    	DCD	0x00100c12   ;0x0010.0000 --> 0x2010.0000	
    	DCD	0x00200c12   ;0x0020.0000 --> 0x2020.0000	
    	DCD	0x00300c12   ;0x0030.0000 --> 0x2030.0000	

		;--------------------------------------------------------------------------------
		;	Dummy  5M~256M   (252M) 0x2040.0000~0x2fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x4040000c
		WHILE	XCount	<	0x50000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
;    	S3C2400 External FLASH FLASH #2 (Bank 1,nGCS1)
;    	Internal ROM Booting (128K Byte) , 0x0200.0000 ~ 0x0201.FFFF (ATF29LV1024)
;    	External ROM Booting (  4M Byte) , 0x0200.0000 ~ 0x023F.FFFF (Supports HY29LV320)
;		None Cached and Write Buffered
;========================================================================================
    	DCD	0x02000c12   ;0x0200.0000 --> 0x3000.0000	
    	DCD	0x02100c12   ;0x0210.0000 --> 0x3010.0000	
    	DCD	0x02200c12   ;0x0220.0000 --> 0x3020.0000	
    	DCD	0x02300c12   ;0x0230.0000 --> 0x3030.0000	

		;--------------------------------------------------------------------------------
		;	Dummy  5M~256M   (252M) 0x3040.0000~0x3fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x5040000c
		WHILE	XCount	<	0x60000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
;    	S3C2400 User defined I/O ADDRESS (Bank 5,nGCS5)
;		None Cached and Write Buffered
;========================================================================================
    	DCD	0x0a000c12   ;0x0a00.0000 --> 0x4000.0000	

		;--------------------------------------------------------------------------------
		;	Dummy  2M~256M   (255M) 0x4010.0000~0x4fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x6010000c
		WHILE	XCount	<	0x70000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
; 		S3C2400 Unused Area  (Bank 2,nGCS2)
; 		None Cached and Write Buffered
;========================================================================================
		;	SDRAM BANK (GCS2 : 32M) 0x0400.0000~0x05ff.ffff --> 0x5000.0000~0x51ff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x04000c12
		WHILE	XCount	<	0x06000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

		;--------------------------------------------------------------------------------
		;	Dummy 33M~256M   (224M) 0x4200.0000~0x4fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x7200000c
		WHILE	XCount	<	0x80000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
; 		S3C2400 Unused Area  (Bank 3,nGCS3)
; 		None Cached and Write Buffered
;========================================================================================
		;	SDRAM BANK (GCS3 : 32M) 0x0600.0000~0x07ff.ffff : 0x6000.0000~0x61ff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x06000c12
		WHILE	XCount	<	0x08000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

		;--------------------------------------------------------------------------------
		;	Dummy 33M~256M   (224M) 0x6200.0000~0x6fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x8200000c
		WHILE	XCount	<	0x90000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


;========================================================================================
; 		S3C2400 Unused Area  (Bank 4,nGCS4)
; 		None Cached and Write Buffered
;========================================================================================
		;	SDRAM BANK (GCS4 : 32M) 0x0800.0000~0x09ff.ffff : 0x7000.0000~0x71ff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x08000c12
		WHILE	XCount	<	0x0a000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND

		;--------------------------------------------------------------------------------
		;	Dummy 33M~256M   (224M) 0x7200.0000~0x7fff.ffff
		;--------------------------------------------------------------------------------
XCount	SETA	0x9200000c
		WHILE	XCount	<	0xa0000000
		DCD		XCount
XCount	SETA	XCount	+	0x00100000
		WEND


    	END