os_cpu_a.s

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		add		r2, r2, r3					; Enlarge Code Area to cover RW Area

COPY_CODE
		cmp		r0, r2
		ldrne	r3, [r0], #4
		strne	r3, [r1], #4
		bne		COPY_CODE

;--------------------------------------------------------------------------------
;   Setting MMU
;   Page Table is fetched from MMU.S
;--------------------------------------------------------------------------------
		ldr		r0, =0x00000000
		mcr		p15, 0, r0, c5, c0
		mcr		p15, 0, r0, c7, c0

;--------------------------------------------------------------------------------
; 	Set user mode access for all 16 domains.
;--------------------------------------------------------------------------------
		ldr		r0, =0x55555555
		mcr		p15, 0, r0, c3, c0

;--------------------------------------------------------------------------------
; 	Tell the MMU where to find the page table.
;--------------------------------------------------------------------------------
		IMPORT	PageTable

		ldr		r0, =PageTable
		mcr		p15, 0, r0, c2, c0

;--------------------------------------------------------------------------------
; 	Enable the MMU.
;--------------------------------------------------------------------------------
		ldr		r0, =0x0000007d
		mcr		p15, 0, r0, c1, c0

;--------------------------------------------------------------------------------
; 	There should always be two NOP instructions following the enable or
; 	disable of the MMU.
;--------------------------------------------------------------------------------
		mov		r0, r0
		mov		r0, r0
	
;--------------------------------------------------------------------------------
;	Variable Area of C code Initialization
;--------------------------------------------------------------------------------

		IMPORT	|Image$$RO$$Limit|		; End of ROM code (=start of ROM data)
		IMPORT	|Image$$RW$$Base|		; Base of RAM to initialise
		IMPORT	|Image$$ZI$$Base|		; Base and limit of area
		IMPORT	|Image$$ZI$$Limit|		; to zero initialise

		ldr		r0, =|Image$$RO$$Limit|	; Get pointer to ROM data
		ldr		r1, =|Image$$RW$$Base|	; and RAM copy
		ldr		r3, =|Image$$ZI$$Base|	; Zero init base => top of initialised data
		cmp		r0, r1					; Check that they are different
		beq		%1

0		cmp		r1, r3					; Copy init data
		ldrcc	r2, [r0], #4
		strcc	r2, [r1], #4
		bcc		%0

1		ldr		r1, =|Image$$ZI$$Limit|	; Top of zero init segment
		mov		r2, #0

2		cmp		r3, r1					; Zero init
		strcc	r2, [r3], #4
		bcc		%2

;--------------------------------------------------------------------------------
; 	Long Jump to External SDRAM
;--------------------------------------------------------------------------------
		IMPORT	entry
		b	entry   ; Jump to C!

;--------------------------------------------------------------------------------
; void enable_irq(void) // Enable irq by resetting "I bit" of CPSR...
;--------------------------------------------------------------------------------
		EXPORT enable_irq

enable_irq
		mrs r1, cpsr		; Copy cpsr to r1
		bic r2, r1, #0x80	; reset cpsr[7] to '0' -> Enable IRQ
		msr cpsr_cf, r2		; restore cpsr

		mov pc, lr			; return to the caller

;--------------------------------------------------------------------------------
; void disable_irq(void) // Disable irq by setting "I bit" of CPSR...
;--------------------------------------------------------------------------------
		EXPORT disable_irq

disable_irq
        mrs r1, cpsr		; Copy cpsr to r1
		orr r2, r1, #0x80	; set cpsr[7] to '1' -> Disable IRQ
		msr cpsr_cf, r2		; restore cpsr
    
		mov pc, lr		; return to the caller

;------------------------------------------------------------------------
;	int splx(int onoff) // IRQ On/Off
;			    // onoff : 1 -> IRQ Disable
;			    // onoff : 0 -> IRQ Enable
	EXPORT  splx
splx
        MRS     r1, cpsr        
        BIC     r2, r1, #0x80   
        CMP     r0, #1          
        ORREQ   r2, r2, #0x80   
        MSR     CPSR_cxsf, r2   
        MOVS    r1, r1, LSL #25 
        MOV     r0, #0          
        MOVCS   r0, #1          
        mov	pc,lr


;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------; 
;	uC/OS Porting Core Function : OSStartHighRdy                          ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

	IMPORT	OSTaskSwHook
	IMPORT	OSRunning
	IMPORT	OSTCBHighRdy

	EXPORT	OSStartHighRdy

OSStartHighRdy  

	BL	OSTaskSwHook			; Call user defined task switch hook

	LDR	r0,=OSRunning			; Indicate that multitasking has started
	MOV	r1,#1
	STRB	r1,[r0]

	LDR	r0,=OSTCBHighRdy		; r0 <= &OSTCBHighRdy
	LDR	r0,[r0]				; r0 <=  OSTCBHighRdy

	LDR	sp,[r0]				; sp <=  OSTCBHighRdy->OSTCBStkPtr

	LDMFD	sp!,{r0}			; restore SP...
	MSR	CPSR_xsf,r0
	LDMFD   sp!,{r0 - r12, lr , pc}		; Load task's context & Run task

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------; 
;	uC/OS Porting Core Function : OSCtxSw                                 ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

	IMPORT	OSTCBCur
	IMPORT	OSTaskSwHook
	IMPORT	OSTCBHighRdy
	IMPORT	OSPrioCur
	IMPORT	OSPrioHighRdy

	EXPORT	OSCtxSw

OSCtxSw	
	STMFD	sp!,{lr}			; push resume address
	STMFD	sp!,{r0 - r12, lr}		; push rest context
	MRS	r0,CPSR
	STMFD	sp!,{r0}			; push CPSR

	LDR	r0,=OSTCBCur			; r0 <= &OSTCBCur
	LDR	r0,[r0]				; r0 <=  OSTCBCur
	STR	sp,[r0]				; OSTCBCur->OSTCBStkPtr = sp

	BL	OSTaskSwHook			; Call user defined task switch hook

	LDR	r0,=OSTCBCur			; r0 <= &OSTCBCur
	LDR	r1,=OSTCBHighRdy		; r1 <= &OSTCBHighRdy
	
	LDR	r2,[r1]				; r2 <=  OSTCBHighRdy
	STR	r2,[r0]				; OSTCBCur = OSTCBHighRdy

	LDR	r0,=OSPrioCur			; r0 <= &OSPrioCur
	LDR	r1,=OSPrioHighRdy		; r1 <= &OSPrioHighRdy
	
	LDRB	r3,[r1]				; r3 <=  OSPrioHighRdy
	STRB	r3,[r0]				; OSPrioCur = OSPrioHighRdy

	LDR	sp,[r2]				; sp <=  OSTCBHighRdy->OSTCBStkPtr

	LDMFD	sp!,{r0}			; restore SP...
	MSR	CPSR_xsf,r0
	LDMFD   sp!,{r0 - r12, lr , pc}		; Load task's context & Run task


;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------; 
;	uC/OS Porting Core Function : OSIntCtxSw                              ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

	IMPORT	OSTCBCur
	IMPORT	OSTaskSwHook
	IMPORT	OSTCBHighRdy
	IMPORT	OSPrioCur
	IMPORT	OSPrioHighRdy

	EXPORT	OSIntCtxSw 

OSIntCtxSw 

	ADD	sp,sp,#4

	LDR	r0,=OSTCBCur			; r0 <= &OSCTBCur
	LDR	r0,[r0]				; r0 <=  OSCTBCur

	STR	sp,[r0]				; OSTCBCur->OSTCBStkPtr = sp
	
	BL	OSTaskSwHook			; Call user defined task switch hook

	LDR	r0,=OSTCBCur			; r0 <= &OSTCBCur
	LDR	r1,=OSTCBHighRdy		; r1 <= &OSTCBHighRdy
	
	LDR	r2,[r1]				; r2 <=  OSTCBHighRdy
	STR	r2,[r0]				; OSTCBCur = OSTCBHighRdy

	LDR	r0,=OSPrioCur			; r0 <= &OSPrioCur
	LDR	r1,=OSPrioHighRdy		; r1 <= &OSPrioHighRdy
	
	LDRB	r3,[r1]				; r3 <=  OSPrioHighRdy
	STRB	r3,[r0]				; OSPrioCur = OSPrioHighRdy

	LDR	sp,[r2]				; sp <=  OSTCBHighRdy->OSTCBStkPtr
	LDMFD	sp!,{r0}			; restore SP...
	MSR	CPSR_xsf,r0
	LDMFD   sp!,{r0 - r12, lr , pc}		; Load task's context & Run task

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;-----------------------------------------------------------------------------; 
;	uC/OS Porting Core Function : OSTickISR                               ;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
	IMPORT	OSIntNesting
	IMPORT	OSTimeTick
	IMPORT	OSIntExit

OSTickISR  

	LDR	r0,=OSIntNesting		; Notify uC/OS-II of ISR
	LDRB	r1,[r0]
	ADD	r1,r1,#1
	STRB	r1,[r0]
	
	BL	OSTimeTick			; Process system tick
        BL	OSIntExit			; Notify uC/OS-II of end of ISR

	LDMFD	sp!,{r0}
	MSR	CPSR_xsf,r0
	LDMFD   sp!,{r0 - r12, lr , pc}      



;--------------------------------------------------------------------------------
;	MEMORY Setting Table.
;--------------------------------------------------------------------------------

SMRDATA DATA

		DCD 0x22011111	; BWSCON B7:32B, B6:32B, B5:8B, B4:16B, B3:16B, B2:16B, B1:16B, B0:16B
		DCD 0x00001f50	; GCS0
		DCD 0x00000700	; GCS1
		DCD 0x00000700	; GCS2
		DCD 0x00000700	; GCS3
		DCD 0x00000700	; GCS4
		DCD 0x00001100	; GCS5
		DCD 0x00018005	; GCS6, SDRAM (MT=3(SDRAM),Trcd=01(3Clock),SCAN=01(9Bit))
		DCD 0x00018005	; GCS7, SDRAM (MT=3(SDRAM),Trcd=01(3Clock),SCAN=01(9Bit))
		DCD 0x00900000 + 192  ;	Refresh(REFEN=1, TREFMD=0,	Trp=3, Trc=5, Tchr=3)
		DCD 0x00000000	; Bank Size, 32MB/32MB
		DCD 0x00000030	; MRSR 6(CL=3)
		DCD 0x00000030	; MRSR 7(CL=3)

;--------------------------------------------------------------------------------
; 	Zero-initialied read/write data area at the end of RAM.
;--------------------------------------------------------------------------------
    	AREA    |Assembly$$endofram|, DATA, READWRITE, NOINIT

;--------------------------------------------------------------------------------
; The following contains the address of the first free word if internal SRAM.
;--------------------------------------------------------------------------------
    	EXPORT  ulEndOfRAM
ulEndOfRAM
    	DCD     0
;--------------------------------------------------------------------------------


	 	END